ADC_CTRL Simulation Results

Wednesday July 03 2024 23:02:32 UTC

GitHub Revision: `e6706fcc7b`

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 8083624550445280117614176890238357255195852125596561370221115831648066795492

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	adc_ctrl_smoke	15.180s	5.518ms	50	50	100.00
V1	csr_hw_reset	adc_ctrl_csr_hw_reset	2.200s	614.240us	5	5	100.00
V1	csr_rw	adc_ctrl_csr_rw	2.150s	561.648us	20	20	100.00
V1	csr_bit_bash	adc_ctrl_csr_bit_bash	2.321m	44.515ms	5	5	100.00
V1	csr_aliasing	adc_ctrl_csr_aliasing	4.210s	968.713us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	adc_ctrl_csr_mem_rw_with_rand_reset	2.300s	608.426us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	adc_ctrl_csr_rw	2.150s	561.648us	20	20	100.00
		adc_ctrl_csr_aliasing	4.210s	968.713us	5	5	100.00
V1		TOTAL			105	105	100.00
V2	filters_polled	adc_ctrl_filters_polled	17.947m	488.903ms	50	50	100.00
V2	filters_polled_fixed	adc_ctrl_filters_polled_fixed	19.687m	492.272ms	50	50	100.00
V2	filters_interrupt	adc_ctrl_filters_interrupt	19.333m	483.562ms	50	50	100.00
V2	filters_interrupt_fixed	adc_ctrl_filters_interrupt_fixed	19.902m	503.554ms	50	50	100.00
V2	filters_wakeup	adc_ctrl_filters_wakeup	22.080m	584.567ms	50	50	100.00
V2	filters_wakeup_fixed	adc_ctrl_filters_wakeup_fixed	23.933m	589.843ms	50	50	100.00
V2	filters_both	adc_ctrl_filters_both	21.275m	540.102ms	49	50	98.00
V2	clock_gating	adc_ctrl_clock_gating	20.372m	594.032ms	50	50	100.00
V2	poweron_counter	adc_ctrl_poweron_counter	13.310s	5.128ms	50	50	100.00
V2	lowpower_counter	adc_ctrl_lowpower_counter	1.764m	47.464ms	50	50	100.00
V2	fsm_reset	adc_ctrl_fsm_reset	11.377m	122.443ms	50	50	100.00
V2	stress_all	adc_ctrl_stress_all	50.202m	2.414s	50	50	100.00
V2	alert_test	adc_ctrl_alert_test	1.800s	508.313us	50	50	100.00
V2	intr_test	adc_ctrl_intr_test	1.830s	533.909us	50	50	100.00
V2	tl_d_oob_addr_access	adc_ctrl_tl_errors	3.640s	541.127us	20	20	100.00
V2	tl_d_illegal_access	adc_ctrl_tl_errors	3.640s	541.127us	20	20	100.00
V2	tl_d_outstanding_access	adc_ctrl_csr_hw_reset	2.200s	614.240us	5	5	100.00
		adc_ctrl_csr_rw	2.150s	561.648us	20	20	100.00
		adc_ctrl_csr_aliasing	4.210s	968.713us	5	5	100.00
		adc_ctrl_same_csr_outstanding	22.190s	5.865ms	20	20	100.00
V2	tl_d_partial_access	adc_ctrl_csr_hw_reset	2.200s	614.240us	5	5	100.00
		adc_ctrl_csr_rw	2.150s	561.648us	20	20	100.00
		adc_ctrl_csr_aliasing	4.210s	968.713us	5	5	100.00
		adc_ctrl_same_csr_outstanding	22.190s	5.865ms	20	20	100.00
V2		TOTAL			739	740	99.86
V2S	tl_intg_err	adc_ctrl_sec_cm	11.280s	4.704ms	5	5	100.00
		adc_ctrl_tl_intg_err	21.220s	8.056ms	20	20	100.00
V2S	sec_cm_bus_integrity	adc_ctrl_tl_intg_err	21.220s	8.056ms	20	20	100.00
V2S		TOTAL			25	25	100.00
V3	stress_all_with_rand_reset	adc_ctrl_stress_all_with_rand_reset	18.358m	823.403ms	50	50	100.00
V3		TOTAL			50	50	100.00
		TOTAL			919	920	99.89

Testplan Progress

Items	Total	Written	Passing	Progress
V1	6	6	6	100.00
V2	16	16	15	93.75
V2S	2	2	2	100.00
V3	1	1	1	100.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
97.76	99.07	96.67	100.00	100.00	98.83	98.33	91.44

Failure Buckets

UVM_FATAL (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue has 1 failures:
- Test adc_ctrl_filters_both has 1 failures.
  - 49.adc_ctrl_filters_both.19439739727570292664245569143039797393348818920626059782767979246642227312596
    Line 357, in log /container/opentitan-public/scratch/os_regression/adc_ctrl-sim-vcs/49.adc_ctrl_filters_both/latest/run.log
```
  UVM_FATAL @ 600000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 600000000000 ps hit, indicating a probable testbench issue
  UVM_INFO @ 600000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

ADC_CTRL Simulation Results

Wednesday July 03 2024 23:02:32 UTC

GitHub Revision: e6706fcc7b

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 8083624550445280117614176890238357255195852125596561370221115831648066795492

Test Results

Testplan Progress

Coverage Results

Coverage Dashboard

Failure Buckets

Past Results

GitHub Revision: `e6706fcc7b`