ADC_CTRL Simulation Results

Thursday July 04 2024 23:02:28 UTC

GitHub Revision: `3e678c112b`

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 94940390549829454688103081328166376218078465228811124044523808815554354133843

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	adc_ctrl_smoke	15.670s	5.806ms	50	50	100.00
V1	csr_hw_reset	adc_ctrl_csr_hw_reset	2.590s	748.558us	5	5	100.00
V1	csr_rw	adc_ctrl_csr_rw	2.100s	566.972us	20	20	100.00
V1	csr_bit_bash	adc_ctrl_csr_bit_bash	2.148m	26.558ms	5	5	100.00
V1	csr_aliasing	adc_ctrl_csr_aliasing	4.940s	1.253ms	5	5	100.00
V1	csr_mem_rw_with_rand_reset	adc_ctrl_csr_mem_rw_with_rand_reset	2.100s	524.793us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	adc_ctrl_csr_rw	2.100s	566.972us	20	20	100.00
		adc_ctrl_csr_aliasing	4.940s	1.253ms	5	5	100.00
V1		TOTAL			105	105	100.00
V2	filters_polled	adc_ctrl_filters_polled	18.548m	496.722ms	50	50	100.00
V2	filters_polled_fixed	adc_ctrl_filters_polled_fixed	19.613m	492.984ms	50	50	100.00
V2	filters_interrupt	adc_ctrl_filters_interrupt	19.509m	488.797ms	50	50	100.00
V2	filters_interrupt_fixed	adc_ctrl_filters_interrupt_fixed	18.914m	490.368ms	50	50	100.00
V2	filters_wakeup	adc_ctrl_filters_wakeup	23.955m	643.309ms	50	50	100.00
V2	filters_wakeup_fixed	adc_ctrl_filters_wakeup_fixed	24.873m	603.408ms	50	50	100.00
V2	filters_both	adc_ctrl_filters_both	22.955m	600.000ms	49	50	98.00
V2	clock_gating	adc_ctrl_clock_gating	19.679m	531.624ms	50	50	100.00
V2	poweron_counter	adc_ctrl_poweron_counter	12.430s	5.372ms	50	50	100.00
V2	lowpower_counter	adc_ctrl_lowpower_counter	1.698m	43.289ms	50	50	100.00
V2	fsm_reset	adc_ctrl_fsm_reset	12.095m	132.945ms	50	50	100.00
V2	stress_all	adc_ctrl_stress_all	31.149m	1.722s	50	50	100.00
V2	alert_test	adc_ctrl_alert_test	1.820s	513.767us	50	50	100.00
V2	intr_test	adc_ctrl_intr_test	1.890s	493.543us	50	50	100.00
V2	tl_d_oob_addr_access	adc_ctrl_tl_errors	4.160s	642.383us	20	20	100.00
V2	tl_d_illegal_access	adc_ctrl_tl_errors	4.160s	642.383us	20	20	100.00
V2	tl_d_outstanding_access	adc_ctrl_csr_hw_reset	2.590s	748.558us	5	5	100.00
		adc_ctrl_csr_rw	2.100s	566.972us	20	20	100.00
		adc_ctrl_csr_aliasing	4.940s	1.253ms	5	5	100.00
		adc_ctrl_same_csr_outstanding	21.130s	4.019ms	20	20	100.00
V2	tl_d_partial_access	adc_ctrl_csr_hw_reset	2.590s	748.558us	5	5	100.00
		adc_ctrl_csr_rw	2.100s	566.972us	20	20	100.00
		adc_ctrl_csr_aliasing	4.940s	1.253ms	5	5	100.00
		adc_ctrl_same_csr_outstanding	21.130s	4.019ms	20	20	100.00
V2		TOTAL			739	740	99.86
V2S	tl_intg_err	adc_ctrl_sec_cm	16.610s	7.901ms	5	5	100.00
		adc_ctrl_tl_intg_err	21.950s	8.768ms	20	20	100.00
V2S	sec_cm_bus_integrity	adc_ctrl_tl_intg_err	21.950s	8.768ms	20	20	100.00
V2S		TOTAL			25	25	100.00
V3	stress_all_with_rand_reset	adc_ctrl_stress_all_with_rand_reset	10.149m	753.290ms	49	50	98.00
V3		TOTAL			49	50	98.00
		TOTAL			918	920	99.78

Testplan Progress

Items	Total	Written	Passing	Progress
V1	6	6	6	100.00
V2	16	16	15	93.75
V2S	2	2	2	100.00
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
97.68	99.07	96.67	100.00	100.00	98.83	98.33	90.87

Failure Buckets

UVM_FATAL (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue has 1 failures:
- Test adc_ctrl_filters_both has 1 failures.
  - 7.adc_ctrl_filters_both.112608185836195885109861262900777888579536160658662493439393535378308508663556
    Line 357, in log /container/opentitan-public/scratch/os_regression/adc_ctrl-sim-vcs/7.adc_ctrl_filters_both/latest/run.log
```
  UVM_FATAL @ 600000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 600000000000 ps hit, indicating a probable testbench issue
  UVM_INFO @ 600000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
Offending '(np_sample_cnt_q == '0)' has 1 failures:
- Test adc_ctrl_stress_all_with_rand_reset has 1 failures.
  - 12.adc_ctrl_stress_all_with_rand_reset.42021172857743805710410645983820948665158496688737779558634237137801718884701
    Line 449, in log /container/opentitan-public/scratch/os_regression/adc_ctrl-sim-vcs/12.adc_ctrl_stress_all_with_rand_reset/latest/run.log
```
      Offending '(np_sample_cnt_q == '0)'
  UVM_ERROR @ 51195038156 ps: (adc_ctrl_fsm.sv:384) [ASSERT FAILED] NpCntClrPwrDn_A
  UVM_INFO @ 51195038156 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

ADC_CTRL Simulation Results

Thursday July 04 2024 23:02:28 UTC

GitHub Revision: 3e678c112b

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 94940390549829454688103081328166376218078465228811124044523808815554354133843

Test Results

Testplan Progress

Coverage Results

Coverage Dashboard

Failure Buckets

Past Results

GitHub Revision: `3e678c112b`