ADC_CTRL Simulation Results

Friday July 05 2024 23:02:55 UTC

GitHub Revision: 9edf84e236

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 47623749544922802985321435118963335754001495105472137721881337469861493653463

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	adc_ctrl_smoke	15.280s	6.040ms	50	50	100.00
V1	csr_hw_reset	adc_ctrl_csr_hw_reset	3.000s	1.069ms	5	5	100.00
V1	csr_rw	adc_ctrl_csr_rw	1.990s	540.074us	20	20	100.00
V1	csr_bit_bash	adc_ctrl_csr_bit_bash	3.425m	52.954ms	5	5	100.00
V1	csr_aliasing	adc_ctrl_csr_aliasing	3.200s	1.334ms	5	5	100.00
V1	csr_mem_rw_with_rand_reset	adc_ctrl_csr_mem_rw_with_rand_reset	2.140s	490.671us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	adc_ctrl_csr_rw	1.990s	540.074us	20	20	100.00
		adc_ctrl_csr_aliasing	3.200s	1.334ms	5	5	100.00
V1		TOTAL			105	105	100.00
V2	filters_polled	adc_ctrl_filters_polled	19.744m	490.137ms	50	50	100.00
V2	filters_polled_fixed	adc_ctrl_filters_polled_fixed	19.237m	494.893ms	50	50	100.00
V2	filters_interrupt	adc_ctrl_filters_interrupt	19.624m	492.492ms	50	50	100.00
V2	filters_interrupt_fixed	adc_ctrl_filters_interrupt_fixed	17.280m	492.231ms	50	50	100.00
V2	filters_wakeup	adc_ctrl_filters_wakeup	21.804m	544.241ms	50	50	100.00
V2	filters_wakeup_fixed	adc_ctrl_filters_wakeup_fixed	24.295m	602.944ms	50	50	100.00
V2	filters_both	adc_ctrl_filters_both	22.005m	537.127ms	49	50	98.00
V2	clock_gating	adc_ctrl_clock_gating	20.885m	571.868ms	50	50	100.00
V2	poweron_counter	adc_ctrl_poweron_counter	13.610s	5.384ms	50	50	100.00
V2	lowpower_counter	adc_ctrl_lowpower_counter	1.732m	44.765ms	50	50	100.00
V2	fsm_reset	adc_ctrl_fsm_reset	11.614m	127.717ms	50	50	100.00
V2	stress_all	adc_ctrl_stress_all	53.200m	1.403s	50	50	100.00
V2	alert_test	adc_ctrl_alert_test	1.740s	462.261us	50	50	100.00
V2	intr_test	adc_ctrl_intr_test	1.930s	493.234us	50	50	100.00
V2	tl_d_oob_addr_access	adc_ctrl_tl_errors	3.490s	1.200ms	20	20	100.00
V2	tl_d_illegal_access	adc_ctrl_tl_errors	3.490s	1.200ms	20	20	100.00
V2	tl_d_outstanding_access	adc_ctrl_csr_hw_reset	3.000s	1.069ms	5	5	100.00
		adc_ctrl_csr_rw	1.990s	540.074us	20	20	100.00
		adc_ctrl_csr_aliasing	3.200s	1.334ms	5	5	100.00
		adc_ctrl_same_csr_outstanding	18.570s	4.601ms	20	20	100.00
V2	tl_d_partial_access	adc_ctrl_csr_hw_reset	3.000s	1.069ms	5	5	100.00
		adc_ctrl_csr_rw	1.990s	540.074us	20	20	100.00
		adc_ctrl_csr_aliasing	3.200s	1.334ms	5	5	100.00
		adc_ctrl_same_csr_outstanding	18.570s	4.601ms	20	20	100.00
V2		TOTAL			739	740	99.86
V2S	tl_intg_err	adc_ctrl_sec_cm	9.990s	7.836ms	5	5	100.00
		adc_ctrl_tl_intg_err	21.960s	8.118ms	20	20	100.00
V2S	sec_cm_bus_integrity	adc_ctrl_tl_intg_err	21.960s	8.118ms	20	20	100.00
V2S		TOTAL			25	25	100.00
V3	stress_all_with_rand_reset	adc_ctrl_stress_all_with_rand_reset	11.737m	912.883ms	50	50	100.00
V3		TOTAL			50	50	100.00
		TOTAL			919	920	99.89

Testplan Progress

Items	Total	Written	Passing	Progress
V1	6	6	6	100.00
V2	16	16	15	93.75
V2S	2	2	2	100.00
V3	1	1	1	100.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
97.79	99.07	96.67	100.00	100.00	98.83	98.33	91.61

Failure Buckets

• UVM_FATAL (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue has 1 failures:
  • Test adc_ctrl_filters_both has 1 failures.

    • 47.adc_ctrl_filters_both.103937364191034179598598141165517667060089810833512798914845494969578988420096
      Line 357, in log /container/opentitan-public/scratch/os_regression/adc_ctrl-sim-vcs/47.adc_ctrl_filters_both/latest/run.log

        UVM_FATAL @ 600000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 600000000000 ps hit, indicating a probable testbench issue
        UVM_INFO @ 600000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

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