ADC_CTRL Simulation Results

Saturday July 06 2024 23:02:28 UTC

GitHub Revision: c42c47ec2d

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 3200059823452722292543998130245428086525417237473114929151723951411399280153

Test Results

Stage Name Tests Max Job Runtime Simulated Time Passing Total Pass Rate
V1 smoke adc_ctrl_smoke 16.040s 5.985ms 50 50 100.00
V1 csr_hw_reset adc_ctrl_csr_hw_reset 3.460s 1.301ms 5 5 100.00
V1 csr_rw adc_ctrl_csr_rw 2.030s 511.768us 19 20 95.00
V1 csr_bit_bash adc_ctrl_csr_bit_bash 1.957m 49.615ms 5 5 100.00
V1 csr_aliasing adc_ctrl_csr_aliasing 4.560s 871.080us 5 5 100.00
V1 csr_mem_rw_with_rand_reset adc_ctrl_csr_mem_rw_with_rand_reset 2.100s 547.297us 20 20 100.00
V1 regwen_csr_and_corresponding_lockable_csr adc_ctrl_csr_rw 2.030s 511.768us 19 20 95.00
adc_ctrl_csr_aliasing 4.560s 871.080us 5 5 100.00
V1 TOTAL 104 105 99.05
V2 filters_polled adc_ctrl_filters_polled 19.418m 491.935ms 50 50 100.00
V2 filters_polled_fixed adc_ctrl_filters_polled_fixed 19.681m 494.312ms 50 50 100.00
V2 filters_interrupt adc_ctrl_filters_interrupt 20.586m 498.487ms 50 50 100.00
V2 filters_interrupt_fixed adc_ctrl_filters_interrupt_fixed 20.419m 506.049ms 50 50 100.00
V2 filters_wakeup adc_ctrl_filters_wakeup 22.759m 552.949ms 50 50 100.00
V2 filters_wakeup_fixed adc_ctrl_filters_wakeup_fixed 23.276m 609.500ms 50 50 100.00
V2 filters_both adc_ctrl_filters_both 21.187m 523.280ms 50 50 100.00
V2 clock_gating adc_ctrl_clock_gating 20.490m 535.238ms 50 50 100.00
V2 poweron_counter adc_ctrl_poweron_counter 14.660s 5.538ms 50 50 100.00
V2 lowpower_counter adc_ctrl_lowpower_counter 1.734m 46.072ms 50 50 100.00
V2 fsm_reset adc_ctrl_fsm_reset 11.480m 127.159ms 50 50 100.00
V2 stress_all adc_ctrl_stress_all 40.042m 926.546ms 50 50 100.00
V2 alert_test adc_ctrl_alert_test 1.740s 519.811us 50 50 100.00
V2 intr_test adc_ctrl_intr_test 1.980s 512.859us 50 50 100.00
V2 tl_d_oob_addr_access adc_ctrl_tl_errors 4.070s 643.341us 20 20 100.00
V2 tl_d_illegal_access adc_ctrl_tl_errors 4.070s 643.341us 20 20 100.00
V2 tl_d_outstanding_access adc_ctrl_csr_hw_reset 3.460s 1.301ms 5 5 100.00
adc_ctrl_csr_rw 2.030s 511.768us 19 20 95.00
adc_ctrl_csr_aliasing 4.560s 871.080us 5 5 100.00
adc_ctrl_same_csr_outstanding 20.280s 5.028ms 20 20 100.00
V2 tl_d_partial_access adc_ctrl_csr_hw_reset 3.460s 1.301ms 5 5 100.00
adc_ctrl_csr_rw 2.030s 511.768us 19 20 95.00
adc_ctrl_csr_aliasing 4.560s 871.080us 5 5 100.00
adc_ctrl_same_csr_outstanding 20.280s 5.028ms 20 20 100.00
V2 TOTAL 740 740 100.00
V2S tl_intg_err adc_ctrl_sec_cm 15.890s 7.792ms 5 5 100.00
adc_ctrl_tl_intg_err 21.690s 7.587ms 20 20 100.00
V2S sec_cm_bus_integrity adc_ctrl_tl_intg_err 21.690s 7.587ms 20 20 100.00
V2S TOTAL 25 25 100.00
V3 stress_all_with_rand_reset adc_ctrl_stress_all_with_rand_reset 15.832m 620.279ms 50 50 100.00
V3 TOTAL 50 50 100.00
TOTAL 919 920 99.89

Testplan Progress

Items Total Written Passing Progress
V1 6 6 5 83.33
V2 16 16 16 100.00
V2S 2 2 2 100.00
V3 1 1 1 100.00

Coverage Results

Coverage Dashboard

SCORE LINE COND TOGGLE FSM BRANCH ASSERT GROUP
97.84 99.07 96.67 100.00 100.00 98.83 98.33 91.96

Failure Buckets

Past Results