ADC_CTRL Simulation Results

Sunday July 07 2024 23:02:38 UTC

GitHub Revision: `2e5d86c9b5`

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 75221189197949424635294305394615322888112457483844341597147780944629972574676

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	adc_ctrl_smoke	15.070s	6.158ms	50	50	100.00
V1	csr_hw_reset	adc_ctrl_csr_hw_reset	2.240s	1.295ms	5	5	100.00
V1	csr_rw	adc_ctrl_csr_rw	1.910s	502.148us	20	20	100.00
V1	csr_bit_bash	adc_ctrl_csr_bit_bash	1.540m	44.175ms	5	5	100.00
V1	csr_aliasing	adc_ctrl_csr_aliasing	4.950s	1.061ms	5	5	100.00
V1	csr_mem_rw_with_rand_reset	adc_ctrl_csr_mem_rw_with_rand_reset	2.370s	567.576us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	adc_ctrl_csr_rw	1.910s	502.148us	20	20	100.00
		adc_ctrl_csr_aliasing	4.950s	1.061ms	5	5	100.00
V1		TOTAL			105	105	100.00
V2	filters_polled	adc_ctrl_filters_polled	19.184m	490.662ms	50	50	100.00
V2	filters_polled_fixed	adc_ctrl_filters_polled_fixed	19.132m	491.147ms	50	50	100.00
V2	filters_interrupt	adc_ctrl_filters_interrupt	19.572m	485.090ms	50	50	100.00
V2	filters_interrupt_fixed	adc_ctrl_filters_interrupt_fixed	19.384m	495.480ms	50	50	100.00
V2	filters_wakeup	adc_ctrl_filters_wakeup	21.916m	542.234ms	50	50	100.00
V2	filters_wakeup_fixed	adc_ctrl_filters_wakeup_fixed	24.573m	609.595ms	50	50	100.00
V2	filters_both	adc_ctrl_filters_both	23.333m	600.000ms	49	50	98.00
V2	clock_gating	adc_ctrl_clock_gating	19.514m	520.312ms	50	50	100.00
V2	poweron_counter	adc_ctrl_poweron_counter	12.850s	5.470ms	50	50	100.00
V2	lowpower_counter	adc_ctrl_lowpower_counter	1.655m	43.933ms	50	50	100.00
V2	fsm_reset	adc_ctrl_fsm_reset	11.804m	123.079ms	50	50	100.00
V2	stress_all	adc_ctrl_stress_all	56.226m	1.666s	50	50	100.00
V2	alert_test	adc_ctrl_alert_test	1.850s	493.259us	50	50	100.00
V2	intr_test	adc_ctrl_intr_test	1.890s	528.143us	50	50	100.00
V2	tl_d_oob_addr_access	adc_ctrl_tl_errors	3.650s	644.595us	20	20	100.00
V2	tl_d_illegal_access	adc_ctrl_tl_errors	3.650s	644.595us	20	20	100.00
V2	tl_d_outstanding_access	adc_ctrl_csr_hw_reset	2.240s	1.295ms	5	5	100.00
		adc_ctrl_csr_rw	1.910s	502.148us	20	20	100.00
		adc_ctrl_csr_aliasing	4.950s	1.061ms	5	5	100.00
		adc_ctrl_same_csr_outstanding	20.450s	5.324ms	20	20	100.00
V2	tl_d_partial_access	adc_ctrl_csr_hw_reset	2.240s	1.295ms	5	5	100.00
		adc_ctrl_csr_rw	1.910s	502.148us	20	20	100.00
		adc_ctrl_csr_aliasing	4.950s	1.061ms	5	5	100.00
		adc_ctrl_same_csr_outstanding	20.450s	5.324ms	20	20	100.00
V2		TOTAL			739	740	99.86
V2S	tl_intg_err	adc_ctrl_sec_cm	19.630s	8.235ms	5	5	100.00
		adc_ctrl_tl_intg_err	23.720s	8.389ms	20	20	100.00
V2S	sec_cm_bus_integrity	adc_ctrl_tl_intg_err	23.720s	8.389ms	20	20	100.00
V2S		TOTAL			25	25	100.00
V3	stress_all_with_rand_reset	adc_ctrl_stress_all_with_rand_reset	14.365m	1.302s	48	50	96.00
V3		TOTAL			48	50	96.00
		TOTAL			917	920	99.67

Testplan Progress

Items	Total	Written	Passing	Progress
V1	6	6	6	100.00
V2	16	16	15	93.75
V2S	2	2	2	100.00
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
97.82	99.07	96.67	100.00	100.00	98.83	98.33	91.84

Failure Buckets

Offending '(np_sample_cnt_q == '0)' has 1 failures:
- Test adc_ctrl_stress_all_with_rand_reset has 1 failures.
  - 2.adc_ctrl_stress_all_with_rand_reset.63338613306232605343750643924886713989472069480133468355901730156926430839161
    Line 594, in log /container/opentitan-public/scratch/os_regression/adc_ctrl-sim-vcs/2.adc_ctrl_stress_all_with_rand_reset/latest/run.log
```
      Offending '(np_sample_cnt_q == '0)'
  UVM_ERROR @ 314380455025 ps: (adc_ctrl_fsm.sv:384) [ASSERT FAILED] NpCntClrPwrDn_A
  UVM_INFO @ 314380455025 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (adc_ctrl_scoreboard.sv:405) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) reg name: adc_ctrl_reg_block.filter_status has 1 failures:
- Test adc_ctrl_stress_all_with_rand_reset has 1 failures.
  - 18.adc_ctrl_stress_all_with_rand_reset.7928318789792004432827792623068048880360672582056420863553365423312187999959
    Line 353, in log /container/opentitan-public/scratch/os_regression/adc_ctrl-sim-vcs/18.adc_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 6593240248 ps: (adc_ctrl_scoreboard.sv:405) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (0 [0x0] vs 80 [0x50]) reg name: adc_ctrl_reg_block.filter_status
  UVM_INFO @ 6593240248 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue has 1 failures:
- Test adc_ctrl_filters_both has 1 failures.
  - 26.adc_ctrl_filters_both.93446879185584835552851071880327000612445444225715598345609342091573772985476
    Line 357, in log /container/opentitan-public/scratch/os_regression/adc_ctrl-sim-vcs/26.adc_ctrl_filters_both/latest/run.log
```
  UVM_FATAL @ 600000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 600000000000 ps hit, indicating a probable testbench issue
  UVM_INFO @ 600000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

ADC_CTRL Simulation Results

Sunday July 07 2024 23:02:38 UTC

GitHub Revision: 2e5d86c9b5

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 75221189197949424635294305394615322888112457483844341597147780944629972574676

Test Results

Testplan Progress

Coverage Results

Coverage Dashboard

Failure Buckets

Past Results

GitHub Revision: `2e5d86c9b5`