ADC_CTRL Simulation Results

Tuesday July 09 2024 23:02:48 UTC

GitHub Revision: `6a84251492`

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 61727890964832844865465694323650730626175387240181955975848876152363892893427

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	adc_ctrl_smoke	15.860s	6.072ms	50	50	100.00
V1	csr_hw_reset	adc_ctrl_csr_hw_reset	2.930s	1.034ms	5	5	100.00
V1	csr_rw	adc_ctrl_csr_rw	2.020s	537.387us	20	20	100.00
V1	csr_bit_bash	adc_ctrl_csr_bit_bash	1.290m	50.526ms	5	5	100.00
V1	csr_aliasing	adc_ctrl_csr_aliasing	2.960s	852.410us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	adc_ctrl_csr_mem_rw_with_rand_reset	2.290s	536.535us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	adc_ctrl_csr_rw	2.020s	537.387us	20	20	100.00
		adc_ctrl_csr_aliasing	2.960s	852.410us	5	5	100.00
V1		TOTAL			105	105	100.00
V2	filters_polled	adc_ctrl_filters_polled	19.804m	499.716ms	50	50	100.00
V2	filters_polled_fixed	adc_ctrl_filters_polled_fixed	19.472m	496.914ms	50	50	100.00
V2	filters_interrupt	adc_ctrl_filters_interrupt	20.053m	503.403ms	50	50	100.00
V2	filters_interrupt_fixed	adc_ctrl_filters_interrupt_fixed	19.732m	497.638ms	50	50	100.00
V2	filters_wakeup	adc_ctrl_filters_wakeup	22.965m	588.615ms	50	50	100.00
V2	filters_wakeup_fixed	adc_ctrl_filters_wakeup_fixed	24.231m	603.938ms	50	50	100.00
V2	filters_both	adc_ctrl_filters_both	21.826m	534.446ms	50	50	100.00
V2	clock_gating	adc_ctrl_clock_gating	18.936m	491.375ms	50	50	100.00
V2	poweron_counter	adc_ctrl_poweron_counter	13.020s	5.225ms	50	50	100.00
V2	lowpower_counter	adc_ctrl_lowpower_counter	1.912m	48.025ms	50	50	100.00
V2	fsm_reset	adc_ctrl_fsm_reset	12.011m	133.992ms	50	50	100.00
V2	stress_all	adc_ctrl_stress_all	19.405m	548.256ms	50	50	100.00
V2	alert_test	adc_ctrl_alert_test	1.830s	514.940us	50	50	100.00
V2	intr_test	adc_ctrl_intr_test	1.760s	523.180us	50	50	100.00
V2	tl_d_oob_addr_access	adc_ctrl_tl_errors	4.210s	626.590us	20	20	100.00
V2	tl_d_illegal_access	adc_ctrl_tl_errors	4.210s	626.590us	20	20	100.00
V2	tl_d_outstanding_access	adc_ctrl_csr_hw_reset	2.930s	1.034ms	5	5	100.00
		adc_ctrl_csr_rw	2.020s	537.387us	20	20	100.00
		adc_ctrl_csr_aliasing	2.960s	852.410us	5	5	100.00
		adc_ctrl_same_csr_outstanding	20.750s	5.215ms	20	20	100.00
V2	tl_d_partial_access	adc_ctrl_csr_hw_reset	2.930s	1.034ms	5	5	100.00
		adc_ctrl_csr_rw	2.020s	537.387us	20	20	100.00
		adc_ctrl_csr_aliasing	2.960s	852.410us	5	5	100.00
		adc_ctrl_same_csr_outstanding	20.750s	5.215ms	20	20	100.00
V2		TOTAL			740	740	100.00
V2S	tl_intg_err	adc_ctrl_sec_cm	10.340s	4.287ms	5	5	100.00
		adc_ctrl_tl_intg_err	23.480s	8.337ms	20	20	100.00
V2S	sec_cm_bus_integrity	adc_ctrl_tl_intg_err	23.480s	8.337ms	20	20	100.00
V2S		TOTAL			25	25	100.00
V3	stress_all_with_rand_reset	adc_ctrl_stress_all_with_rand_reset	14.479m	609.620ms	49	50	98.00
V3		TOTAL			49	50	98.00
		TOTAL			919	920	99.89

Testplan Progress

Items	Total	Written	Passing	Progress
V1	6	6	6	100.00
V2	16	16	16	100.00
V2S	2	2	2	100.00
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
97.75	99.07	96.67	100.00	100.00	98.83	98.33	91.34

Failure Buckets

UVM_ERROR (adc_ctrl_scoreboard.sv:116) [scoreboard] Check failed m_interrupt == ((m_expected_intr_test || |m_expected_adc_intr_status) && intr_en) (* [*] vs * [*]) has 1 failures:
- Test adc_ctrl_stress_all_with_rand_reset has 1 failures.
  - 46.adc_ctrl_stress_all_with_rand_reset.84667440928185557430924392468044296623267960834607590825414511536782448468330
    Line 406, in log /container/opentitan-public/scratch/os_regression/adc_ctrl-sim-vcs/46.adc_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 34267129511 ps: (adc_ctrl_scoreboard.sv:116) [uvm_test_top.env.scoreboard] Check failed m_interrupt == ((m_expected_intr_test || |m_expected_adc_intr_status) && intr_en) (1 [0x1] vs 0 [0x0])
  UVM_INFO @ 34267129511 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

ADC_CTRL Simulation Results

Tuesday July 09 2024 23:02:48 UTC

GitHub Revision: 6a84251492

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 61727890964832844865465694323650730626175387240181955975848876152363892893427

Test Results

Testplan Progress

Coverage Results

Coverage Dashboard

Failure Buckets

Past Results

GitHub Revision: `6a84251492`