ADC_CTRL Simulation Results

Wednesday July 10 2024 23:02:26 UTC

GitHub Revision: 39211701b5

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 52262812535389540465251148247405743574935129745685597413714598750252192397067

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	adc_ctrl_smoke	15.440s	6.041ms	50	50	100.00
V1	csr_hw_reset	adc_ctrl_csr_hw_reset	3.900s	1.277ms	5	5	100.00
V1	csr_rw	adc_ctrl_csr_rw	1.800s	513.241us	20	20	100.00
V1	csr_bit_bash	adc_ctrl_csr_bit_bash	1.564m	40.806ms	5	5	100.00
V1	csr_aliasing	adc_ctrl_csr_aliasing	5.770s	1.194ms	5	5	100.00
V1	csr_mem_rw_with_rand_reset	adc_ctrl_csr_mem_rw_with_rand_reset	2.120s	481.693us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	adc_ctrl_csr_rw	1.800s	513.241us	20	20	100.00
		adc_ctrl_csr_aliasing	5.770s	1.194ms	5	5	100.00
V1		TOTAL			105	105	100.00
V2	filters_polled	adc_ctrl_filters_polled	19.898m	494.657ms	50	50	100.00
V2	filters_polled_fixed	adc_ctrl_filters_polled_fixed	20.187m	496.934ms	50	50	100.00
V2	filters_interrupt	adc_ctrl_filters_interrupt	19.917m	490.341ms	50	50	100.00
V2	filters_interrupt_fixed	adc_ctrl_filters_interrupt_fixed	20.174m	493.281ms	50	50	100.00
V2	filters_wakeup	adc_ctrl_filters_wakeup	24.250m	655.696ms	50	50	100.00
V2	filters_wakeup_fixed	adc_ctrl_filters_wakeup_fixed	22.180m	600.400ms	50	50	100.00
V2	filters_both	adc_ctrl_filters_both	22.870m	600.000ms	49	50	98.00
V2	clock_gating	adc_ctrl_clock_gating	20.408m	523.752ms	50	50	100.00
V2	poweron_counter	adc_ctrl_poweron_counter	13.220s	5.081ms	50	50	100.00
V2	lowpower_counter	adc_ctrl_lowpower_counter	1.812m	45.982ms	50	50	100.00
V2	fsm_reset	adc_ctrl_fsm_reset	11.985m	145.167ms	50	50	100.00
V2	stress_all	adc_ctrl_stress_all	1.230h	1.878s	50	50	100.00
V2	alert_test	adc_ctrl_alert_test	1.880s	520.748us	50	50	100.00
V2	intr_test	adc_ctrl_intr_test	1.930s	526.371us	50	50	100.00
V2	tl_d_oob_addr_access	adc_ctrl_tl_errors	3.740s	467.566us	20	20	100.00
V2	tl_d_illegal_access	adc_ctrl_tl_errors	3.740s	467.566us	20	20	100.00
V2	tl_d_outstanding_access	adc_ctrl_csr_hw_reset	3.900s	1.277ms	5	5	100.00
		adc_ctrl_csr_rw	1.800s	513.241us	20	20	100.00
		adc_ctrl_csr_aliasing	5.770s	1.194ms	5	5	100.00
		adc_ctrl_same_csr_outstanding	15.330s	4.123ms	20	20	100.00
V2	tl_d_partial_access	adc_ctrl_csr_hw_reset	3.900s	1.277ms	5	5	100.00
		adc_ctrl_csr_rw	1.800s	513.241us	20	20	100.00
		adc_ctrl_csr_aliasing	5.770s	1.194ms	5	5	100.00
		adc_ctrl_same_csr_outstanding	15.330s	4.123ms	20	20	100.00
V2		TOTAL			739	740	99.86
V2S	tl_intg_err	adc_ctrl_sec_cm	20.060s	8.163ms	5	5	100.00
		adc_ctrl_tl_intg_err	23.800s	8.722ms	20	20	100.00
V2S	sec_cm_bus_integrity	adc_ctrl_tl_intg_err	23.800s	8.722ms	20	20	100.00
V2S		TOTAL			25	25	100.00
V3	stress_all_with_rand_reset	adc_ctrl_stress_all_with_rand_reset	11.053m	737.317ms	50	50	100.00
V3		TOTAL			50	50	100.00
		TOTAL			919	920	99.89

Testplan Progress

Items	Total	Written	Passing	Progress
V1	6	6	6	100.00
V2	16	16	15	93.75
V2S	2	2	2	100.00
V3	1	1	1	100.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
97.73	99.07	96.67	100.00	100.00	98.83	98.33	91.19

Failure Buckets

• UVM_FATAL (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue has 1 failures:
  • Test adc_ctrl_filters_both has 1 failures.

    • 2.adc_ctrl_filters_both.86335814219414773775295728048796701382316490215203608941949840607048258800480
      Line 357, in log /container/opentitan-public/scratch/os_regression/adc_ctrl-sim-vcs/2.adc_ctrl_filters_both/latest/run.log

        UVM_FATAL @ 600000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 600000000000 ps hit, indicating a probable testbench issue
        UVM_INFO @ 600000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

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