ADC_CTRL Simulation Results

Thursday July 11 2024 23:02:31 UTC

GitHub Revision: edf2fd5092

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 110991919330983905489672005724934609038320729526710604109871030362225161447318

Test Results

Stage Name Tests Max Job Runtime Simulated Time Passing Total Pass Rate
V1 smoke adc_ctrl_smoke 15.450s 6.119ms 50 50 100.00
V1 csr_hw_reset adc_ctrl_csr_hw_reset 2.030s 624.287us 5 5 100.00
V1 csr_rw adc_ctrl_csr_rw 1.820s 467.180us 20 20 100.00
V1 csr_bit_bash adc_ctrl_csr_bit_bash 2.159m 27.001ms 5 5 100.00
V1 csr_aliasing adc_ctrl_csr_aliasing 4.660s 1.199ms 5 5 100.00
V1 csr_mem_rw_with_rand_reset adc_ctrl_csr_mem_rw_with_rand_reset 2.160s 582.446us 20 20 100.00
V1 regwen_csr_and_corresponding_lockable_csr adc_ctrl_csr_rw 1.820s 467.180us 20 20 100.00
adc_ctrl_csr_aliasing 4.660s 1.199ms 5 5 100.00
V1 TOTAL 105 105 100.00
V2 filters_polled adc_ctrl_filters_polled 19.303m 489.147ms 50 50 100.00
V2 filters_polled_fixed adc_ctrl_filters_polled_fixed 19.568m 496.880ms 50 50 100.00
V2 filters_interrupt adc_ctrl_filters_interrupt 19.864m 489.131ms 50 50 100.00
V2 filters_interrupt_fixed adc_ctrl_filters_interrupt_fixed 20.360m 499.655ms 50 50 100.00
V2 filters_wakeup adc_ctrl_filters_wakeup 21.167m 564.705ms 50 50 100.00
V2 filters_wakeup_fixed adc_ctrl_filters_wakeup_fixed 23.561m 588.057ms 50 50 100.00
V2 filters_both adc_ctrl_filters_both 20.998m 528.570ms 50 50 100.00
V2 clock_gating adc_ctrl_clock_gating 23.870m 673.582ms 50 50 100.00
V2 poweron_counter adc_ctrl_poweron_counter 12.090s 5.138ms 50 50 100.00
V2 lowpower_counter adc_ctrl_lowpower_counter 1.858m 47.003ms 50 50 100.00
V2 fsm_reset adc_ctrl_fsm_reset 12.493m 141.591ms 50 50 100.00
V2 stress_all adc_ctrl_stress_all 37.014m 780.414ms 50 50 100.00
V2 alert_test adc_ctrl_alert_test 1.830s 516.819us 50 50 100.00
V2 intr_test adc_ctrl_intr_test 1.830s 531.403us 50 50 100.00
V2 tl_d_oob_addr_access adc_ctrl_tl_errors 3.560s 422.174us 20 20 100.00
V2 tl_d_illegal_access adc_ctrl_tl_errors 3.560s 422.174us 20 20 100.00
V2 tl_d_outstanding_access adc_ctrl_csr_hw_reset 2.030s 624.287us 5 5 100.00
adc_ctrl_csr_rw 1.820s 467.180us 20 20 100.00
adc_ctrl_csr_aliasing 4.660s 1.199ms 5 5 100.00
adc_ctrl_same_csr_outstanding 21.880s 4.493ms 20 20 100.00
V2 tl_d_partial_access adc_ctrl_csr_hw_reset 2.030s 624.287us 5 5 100.00
adc_ctrl_csr_rw 1.820s 467.180us 20 20 100.00
adc_ctrl_csr_aliasing 4.660s 1.199ms 5 5 100.00
adc_ctrl_same_csr_outstanding 21.880s 4.493ms 20 20 100.00
V2 TOTAL 740 740 100.00
V2S tl_intg_err adc_ctrl_sec_cm 18.470s 8.161ms 5 5 100.00
adc_ctrl_tl_intg_err 25.050s 8.899ms 20 20 100.00
V2S sec_cm_bus_integrity adc_ctrl_tl_intg_err 25.050s 8.899ms 20 20 100.00
V2S TOTAL 25 25 100.00
V3 stress_all_with_rand_reset adc_ctrl_stress_all_with_rand_reset 11.595m 540.618ms 50 50 100.00
V3 TOTAL 50 50 100.00
TOTAL 920 920 100.00

Testplan Progress

Items Total Written Passing Progress
V1 6 6 6 100.00
V2 16 16 16 100.00
V2S 2 2 2 100.00
V3 1 1 1 100.00

Coverage Results

Coverage Dashboard

SCORE LINE COND TOGGLE FSM BRANCH ASSERT GROUP
97.73 99.07 96.67 100.00 100.00 98.83 98.33 91.24

Past Results