ADC_CTRL Simulation Results

Friday July 12 2024 23:02:19 UTC

GitHub Revision: `5967df933a`

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 46476530947956470787268850137993439884379231200278174763551439909664842175844

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	adc_ctrl_smoke	15.250s	5.864ms	50	50	100.00
V1	csr_hw_reset	adc_ctrl_csr_hw_reset	3.290s	1.182ms	5	5	100.00
V1	csr_rw	adc_ctrl_csr_rw	2.090s	514.197us	20	20	100.00
V1	csr_bit_bash	adc_ctrl_csr_bit_bash	1.858m	51.777ms	5	5	100.00
V1	csr_aliasing	adc_ctrl_csr_aliasing	3.570s	1.114ms	5	5	100.00
V1	csr_mem_rw_with_rand_reset	adc_ctrl_csr_mem_rw_with_rand_reset	2.240s	571.770us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	adc_ctrl_csr_rw	2.090s	514.197us	20	20	100.00
		adc_ctrl_csr_aliasing	3.570s	1.114ms	5	5	100.00
V1		TOTAL			105	105	100.00
V2	filters_polled	adc_ctrl_filters_polled	18.375m	500.821ms	50	50	100.00
V2	filters_polled_fixed	adc_ctrl_filters_polled_fixed	18.551m	486.578ms	50	50	100.00
V2	filters_interrupt	adc_ctrl_filters_interrupt	19.435m	499.622ms	50	50	100.00
V2	filters_interrupt_fixed	adc_ctrl_filters_interrupt_fixed	19.874m	487.337ms	50	50	100.00
V2	filters_wakeup	adc_ctrl_filters_wakeup	22.325m	585.079ms	50	50	100.00
V2	filters_wakeup_fixed	adc_ctrl_filters_wakeup_fixed	21.265m	579.980ms	50	50	100.00
V2	filters_both	adc_ctrl_filters_both	21.555m	600.000ms	49	50	98.00
V2	clock_gating	adc_ctrl_clock_gating	22.127m	626.556ms	50	50	100.00
V2	poweron_counter	adc_ctrl_poweron_counter	14.980s	5.331ms	50	50	100.00
V2	lowpower_counter	adc_ctrl_lowpower_counter	1.764m	46.339ms	50	50	100.00
V2	fsm_reset	adc_ctrl_fsm_reset	11.725m	134.158ms	50	50	100.00
V2	stress_all	adc_ctrl_stress_all	45.007m	1.207s	50	50	100.00
V2	alert_test	adc_ctrl_alert_test	1.780s	487.654us	50	50	100.00
V2	intr_test	adc_ctrl_intr_test	1.950s	532.257us	50	50	100.00
V2	tl_d_oob_addr_access	adc_ctrl_tl_errors	3.420s	402.768us	20	20	100.00
V2	tl_d_illegal_access	adc_ctrl_tl_errors	3.420s	402.768us	20	20	100.00
V2	tl_d_outstanding_access	adc_ctrl_csr_hw_reset	3.290s	1.182ms	5	5	100.00
		adc_ctrl_csr_rw	2.090s	514.197us	20	20	100.00
		adc_ctrl_csr_aliasing	3.570s	1.114ms	5	5	100.00
		adc_ctrl_same_csr_outstanding	12.090s	5.123ms	20	20	100.00
V2	tl_d_partial_access	adc_ctrl_csr_hw_reset	3.290s	1.182ms	5	5	100.00
		adc_ctrl_csr_rw	2.090s	514.197us	20	20	100.00
		adc_ctrl_csr_aliasing	3.570s	1.114ms	5	5	100.00
		adc_ctrl_same_csr_outstanding	12.090s	5.123ms	20	20	100.00
V2		TOTAL			739	740	99.86
V2S	tl_intg_err	adc_ctrl_sec_cm	20.100s	7.981ms	5	5	100.00
		adc_ctrl_tl_intg_err	20.710s	7.916ms	20	20	100.00
V2S	sec_cm_bus_integrity	adc_ctrl_tl_intg_err	20.710s	7.916ms	20	20	100.00
V2S		TOTAL			25	25	100.00
V3	stress_all_with_rand_reset	adc_ctrl_stress_all_with_rand_reset	17.444m	1.279s	49	50	98.00
V3		TOTAL			49	50	98.00
		TOTAL			918	920	99.78

Testplan Progress

Items	Total	Written	Passing	Progress
V1	6	6	6	100.00
V2	16	16	15	93.75
V2S	2	2	2	100.00
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
97.79	99.07	96.67	100.00	100.00	98.83	98.33	91.66

Failure Buckets

UVM_ERROR (adc_ctrl_scoreboard.sv:405) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) reg name: adc_ctrl_reg_block.filter_status has 1 failures:
- Test adc_ctrl_stress_all_with_rand_reset has 1 failures.
  - 13.adc_ctrl_stress_all_with_rand_reset.102067455642119856742538160122373429966027417154478479960497601482800505802870
    Line 423, in log /container/opentitan-public/scratch/os_regression/adc_ctrl-sim-vcs/13.adc_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 53477668141 ps: (adc_ctrl_scoreboard.sv:405) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (0 [0x0] vs 80 [0x50]) reg name: adc_ctrl_reg_block.filter_status
  UVM_INFO @ 53477668141 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue has 1 failures:
- Test adc_ctrl_filters_both has 1 failures.
  - 38.adc_ctrl_filters_both.81305685208988380633209167628529847218851817390207513246350650406374153402755
    Line 357, in log /container/opentitan-public/scratch/os_regression/adc_ctrl-sim-vcs/38.adc_ctrl_filters_both/latest/run.log
```
  UVM_FATAL @ 600000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 600000000000 ps hit, indicating a probable testbench issue
  UVM_INFO @ 600000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

ADC_CTRL Simulation Results

Friday July 12 2024 23:02:19 UTC

GitHub Revision: 5967df933a

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 46476530947956470787268850137993439884379231200278174763551439909664842175844

Test Results

Testplan Progress

Coverage Results

Coverage Dashboard

Failure Buckets

Past Results

GitHub Revision: `5967df933a`