ADC_CTRL Simulation Results

Saturday July 13 2024 23:02:33 UTC

GitHub Revision: `d51405297e`

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 101086804359139103922259090811397817605469534164678958852189348539757618502888

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	adc_ctrl_smoke	15.670s	5.927ms	50	50	100.00
V1	csr_hw_reset	adc_ctrl_csr_hw_reset	2.240s	1.311ms	5	5	100.00
V1	csr_rw	adc_ctrl_csr_rw	2.110s	492.879us	20	20	100.00
V1	csr_bit_bash	adc_ctrl_csr_bit_bash	55.210s	26.498ms	5	5	100.00
V1	csr_aliasing	adc_ctrl_csr_aliasing	4.810s	859.512us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	adc_ctrl_csr_mem_rw_with_rand_reset	2.220s	586.634us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	adc_ctrl_csr_rw	2.110s	492.879us	20	20	100.00
		adc_ctrl_csr_aliasing	4.810s	859.512us	5	5	100.00
V1		TOTAL			105	105	100.00
V2	filters_polled	adc_ctrl_filters_polled	18.979m	492.671ms	50	50	100.00
V2	filters_polled_fixed	adc_ctrl_filters_polled_fixed	19.563m	486.899ms	50	50	100.00
V2	filters_interrupt	adc_ctrl_filters_interrupt	19.484m	494.562ms	50	50	100.00
V2	filters_interrupt_fixed	adc_ctrl_filters_interrupt_fixed	20.282m	493.666ms	50	50	100.00
V2	filters_wakeup	adc_ctrl_filters_wakeup	25.164m	668.509ms	50	50	100.00
V2	filters_wakeup_fixed	adc_ctrl_filters_wakeup_fixed	24.207m	626.405ms	50	50	100.00
V2	filters_both	adc_ctrl_filters_both	21.507m	600.000ms	49	50	98.00
V2	clock_gating	adc_ctrl_clock_gating	21.658m	617.579ms	50	50	100.00
V2	poweron_counter	adc_ctrl_poweron_counter	14.690s	5.428ms	50	50	100.00
V2	lowpower_counter	adc_ctrl_lowpower_counter	1.886m	47.471ms	50	50	100.00
V2	fsm_reset	adc_ctrl_fsm_reset	11.679m	129.548ms	50	50	100.00
V2	stress_all	adc_ctrl_stress_all	28.152m	630.681ms	50	50	100.00
V2	alert_test	adc_ctrl_alert_test	1.850s	528.598us	50	50	100.00
V2	intr_test	adc_ctrl_intr_test	1.930s	517.749us	50	50	100.00
V2	tl_d_oob_addr_access	adc_ctrl_tl_errors	3.720s	605.085us	20	20	100.00
V2	tl_d_illegal_access	adc_ctrl_tl_errors	3.720s	605.085us	20	20	100.00
V2	tl_d_outstanding_access	adc_ctrl_csr_hw_reset	2.240s	1.311ms	5	5	100.00
		adc_ctrl_csr_rw	2.110s	492.879us	20	20	100.00
		adc_ctrl_csr_aliasing	4.810s	859.512us	5	5	100.00
		adc_ctrl_same_csr_outstanding	16.490s	4.443ms	20	20	100.00
V2	tl_d_partial_access	adc_ctrl_csr_hw_reset	2.240s	1.311ms	5	5	100.00
		adc_ctrl_csr_rw	2.110s	492.879us	20	20	100.00
		adc_ctrl_csr_aliasing	4.810s	859.512us	5	5	100.00
		adc_ctrl_same_csr_outstanding	16.490s	4.443ms	20	20	100.00
V2		TOTAL			739	740	99.86
V2S	tl_intg_err	adc_ctrl_sec_cm	19.260s	8.364ms	5	5	100.00
		adc_ctrl_tl_intg_err	23.000s	8.681ms	20	20	100.00
V2S	sec_cm_bus_integrity	adc_ctrl_tl_intg_err	23.000s	8.681ms	20	20	100.00
V2S		TOTAL			25	25	100.00
V3	stress_all_with_rand_reset	adc_ctrl_stress_all_with_rand_reset	13.894m	496.727ms	50	50	100.00
V3		TOTAL			50	50	100.00
		TOTAL			919	920	99.89

Testplan Progress

Items	Total	Written	Passing	Progress
V1	6	6	6	100.00
V2	16	16	15	93.75
V2S	2	2	2	100.00
V3	1	1	1	100.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
97.73	99.07	96.67	100.00	100.00	98.83	98.33	91.19

Failure Buckets

UVM_FATAL (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue has 1 failures:
- Test adc_ctrl_filters_both has 1 failures.
  - 22.adc_ctrl_filters_both.81884431766948564121515061439990278578374181079641803632775114270181126026293
    Line 357, in log /container/opentitan-public/scratch/os_regression/adc_ctrl-sim-vcs/22.adc_ctrl_filters_both/latest/run.log
```
  UVM_FATAL @ 600000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 600000000000 ps hit, indicating a probable testbench issue
  UVM_INFO @ 600000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

ADC_CTRL Simulation Results

Saturday July 13 2024 23:02:33 UTC

GitHub Revision: d51405297e

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 101086804359139103922259090811397817605469534164678958852189348539757618502888

Test Results

Testplan Progress

Coverage Results

Coverage Dashboard

Failure Buckets

Past Results

GitHub Revision: `d51405297e`