ADC_CTRL Simulation Results

Sunday July 14 2024 23:02:31 UTC

GitHub Revision: c04cc5d074

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 63544391231451201456762274895161998707503467555380647510071702152169450996489

Test Results

Stage Name Tests Max Job Runtime Simulated Time Passing Total Pass Rate
V1 smoke adc_ctrl_smoke 14.970s 5.799ms 50 50 100.00
V1 csr_hw_reset adc_ctrl_csr_hw_reset 2.950s 1.006ms 5 5 100.00
V1 csr_rw adc_ctrl_csr_rw 2.010s 536.925us 20 20 100.00
V1 csr_bit_bash adc_ctrl_csr_bit_bash 1.493m 26.247ms 5 5 100.00
V1 csr_aliasing adc_ctrl_csr_aliasing 5.780s 1.015ms 5 5 100.00
V1 csr_mem_rw_with_rand_reset adc_ctrl_csr_mem_rw_with_rand_reset 2.290s 601.074us 20 20 100.00
V1 regwen_csr_and_corresponding_lockable_csr adc_ctrl_csr_rw 2.010s 536.925us 20 20 100.00
adc_ctrl_csr_aliasing 5.780s 1.015ms 5 5 100.00
V1 TOTAL 105 105 100.00
V2 filters_polled adc_ctrl_filters_polled 18.838m 487.520ms 50 50 100.00
V2 filters_polled_fixed adc_ctrl_filters_polled_fixed 18.618m 502.538ms 50 50 100.00
V2 filters_interrupt adc_ctrl_filters_interrupt 20.408m 495.958ms 50 50 100.00
V2 filters_interrupt_fixed adc_ctrl_filters_interrupt_fixed 19.601m 494.389ms 50 50 100.00
V2 filters_wakeup adc_ctrl_filters_wakeup 23.089m 624.328ms 50 50 100.00
V2 filters_wakeup_fixed adc_ctrl_filters_wakeup_fixed 23.461m 611.072ms 50 50 100.00
V2 filters_both adc_ctrl_filters_both 20.395m 520.521ms 50 50 100.00
V2 clock_gating adc_ctrl_clock_gating 23.269m 590.893ms 50 50 100.00
V2 poweron_counter adc_ctrl_poweron_counter 12.920s 5.333ms 50 50 100.00
V2 lowpower_counter adc_ctrl_lowpower_counter 1.731m 42.976ms 50 50 100.00
V2 fsm_reset adc_ctrl_fsm_reset 11.626m 126.283ms 50 50 100.00
V2 stress_all adc_ctrl_stress_all 28.775m 559.483ms 50 50 100.00
V2 alert_test adc_ctrl_alert_test 1.800s 525.295us 50 50 100.00
V2 intr_test adc_ctrl_intr_test 1.970s 520.191us 50 50 100.00
V2 tl_d_oob_addr_access adc_ctrl_tl_errors 3.670s 581.072us 20 20 100.00
V2 tl_d_illegal_access adc_ctrl_tl_errors 3.670s 581.072us 20 20 100.00
V2 tl_d_outstanding_access adc_ctrl_csr_hw_reset 2.950s 1.006ms 5 5 100.00
adc_ctrl_csr_rw 2.010s 536.925us 20 20 100.00
adc_ctrl_csr_aliasing 5.780s 1.015ms 5 5 100.00
adc_ctrl_same_csr_outstanding 14.320s 4.014ms 20 20 100.00
V2 tl_d_partial_access adc_ctrl_csr_hw_reset 2.950s 1.006ms 5 5 100.00
adc_ctrl_csr_rw 2.010s 536.925us 20 20 100.00
adc_ctrl_csr_aliasing 5.780s 1.015ms 5 5 100.00
adc_ctrl_same_csr_outstanding 14.320s 4.014ms 20 20 100.00
V2 TOTAL 740 740 100.00
V2S tl_intg_err adc_ctrl_sec_cm 19.320s 8.365ms 5 5 100.00
adc_ctrl_tl_intg_err 22.470s 8.785ms 20 20 100.00
V2S sec_cm_bus_integrity adc_ctrl_tl_intg_err 22.470s 8.785ms 20 20 100.00
V2S TOTAL 25 25 100.00
V3 stress_all_with_rand_reset adc_ctrl_stress_all_with_rand_reset 23.930m 3.183s 50 50 100.00
V3 TOTAL 50 50 100.00
TOTAL 920 920 100.00

Testplan Progress

Items Total Written Passing Progress
V1 6 6 6 100.00
V2 16 16 16 100.00
V2S 2 2 2 100.00
V3 1 1 1 100.00

Coverage Results

Coverage Dashboard

SCORE LINE COND TOGGLE FSM BRANCH ASSERT GROUP
97.74 99.07 96.67 100.00 100.00 98.83 98.33 91.29

Past Results