ADC_CTRL Simulation Results

Monday July 15 2024 23:02:37 UTC

GitHub Revision: a04e34f557

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 78455839157994684327892029952813991699715169368132023215715425571513813941951

Test Results

Stage Name Tests Max Job Runtime Simulated Time Passing Total Pass Rate
V1 smoke adc_ctrl_smoke 15.510s 5.870ms 50 50 100.00
V1 csr_hw_reset adc_ctrl_csr_hw_reset 2.310s 728.739us 5 5 100.00
V1 csr_rw adc_ctrl_csr_rw 2.060s 570.403us 20 20 100.00
V1 csr_bit_bash adc_ctrl_csr_bit_bash 2.677m 52.722ms 5 5 100.00
V1 csr_aliasing adc_ctrl_csr_aliasing 5.240s 1.196ms 5 5 100.00
V1 csr_mem_rw_with_rand_reset adc_ctrl_csr_mem_rw_with_rand_reset 2.070s 559.698us 20 20 100.00
V1 regwen_csr_and_corresponding_lockable_csr adc_ctrl_csr_rw 2.060s 570.403us 20 20 100.00
adc_ctrl_csr_aliasing 5.240s 1.196ms 5 5 100.00
V1 TOTAL 105 105 100.00
V2 filters_polled adc_ctrl_filters_polled 19.378m 490.344ms 50 50 100.00
V2 filters_polled_fixed adc_ctrl_filters_polled_fixed 18.177m 492.250ms 50 50 100.00
V2 filters_interrupt adc_ctrl_filters_interrupt 20.089m 494.416ms 50 50 100.00
V2 filters_interrupt_fixed adc_ctrl_filters_interrupt_fixed 19.596m 491.514ms 50 50 100.00
V2 filters_wakeup adc_ctrl_filters_wakeup 21.956m 665.702ms 50 50 100.00
V2 filters_wakeup_fixed adc_ctrl_filters_wakeup_fixed 23.496m 613.749ms 50 50 100.00
V2 filters_both adc_ctrl_filters_both 20.758m 582.281ms 50 50 100.00
V2 clock_gating adc_ctrl_clock_gating 24.490m 626.776ms 50 50 100.00
V2 poweron_counter adc_ctrl_poweron_counter 14.240s 5.779ms 50 50 100.00
V2 lowpower_counter adc_ctrl_lowpower_counter 1.646m 41.514ms 50 50 100.00
V2 fsm_reset adc_ctrl_fsm_reset 12.013m 134.674ms 50 50 100.00
V2 stress_all adc_ctrl_stress_all 35.693m 686.172ms 50 50 100.00
V2 alert_test adc_ctrl_alert_test 1.800s 513.115us 50 50 100.00
V2 intr_test adc_ctrl_intr_test 1.820s 533.348us 50 50 100.00
V2 tl_d_oob_addr_access adc_ctrl_tl_errors 3.570s 857.359us 20 20 100.00
V2 tl_d_illegal_access adc_ctrl_tl_errors 3.570s 857.359us 20 20 100.00
V2 tl_d_outstanding_access adc_ctrl_csr_hw_reset 2.310s 728.739us 5 5 100.00
adc_ctrl_csr_rw 2.060s 570.403us 20 20 100.00
adc_ctrl_csr_aliasing 5.240s 1.196ms 5 5 100.00
adc_ctrl_same_csr_outstanding 20.670s 4.932ms 20 20 100.00
V2 tl_d_partial_access adc_ctrl_csr_hw_reset 2.310s 728.739us 5 5 100.00
adc_ctrl_csr_rw 2.060s 570.403us 20 20 100.00
adc_ctrl_csr_aliasing 5.240s 1.196ms 5 5 100.00
adc_ctrl_same_csr_outstanding 20.670s 4.932ms 20 20 100.00
V2 TOTAL 740 740 100.00
V2S tl_intg_err adc_ctrl_sec_cm 17.890s 8.239ms 5 5 100.00
adc_ctrl_tl_intg_err 22.230s 8.279ms 20 20 100.00
V2S sec_cm_bus_integrity adc_ctrl_tl_intg_err 22.230s 8.279ms 20 20 100.00
V2S TOTAL 25 25 100.00
V3 stress_all_with_rand_reset adc_ctrl_stress_all_with_rand_reset 7.471m 328.235ms 50 50 100.00
V3 TOTAL 50 50 100.00
TOTAL 920 920 100.00

Testplan Progress

Items Total Written Passing Progress
V1 6 6 6 100.00
V2 16 16 16 100.00
V2S 2 2 2 100.00
V3 1 1 1 100.00

Coverage Results

Coverage Dashboard

SCORE LINE COND TOGGLE FSM BRANCH ASSERT GROUP
97.74 99.07 96.67 100.00 100.00 98.83 98.33 91.27

Past Results