ADC_CTRL Simulation Results

Tuesday July 16 2024 23:15:02 UTC

GitHub Revision: `aad711e1bc`

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 38297581588405771015102977205739484163575733999253050480227719508149669635625

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	adc_ctrl_smoke	14.650s	5.921ms	50	50	100.00
V1	csr_hw_reset	adc_ctrl_csr_hw_reset	3.070s	1.153ms	5	5	100.00
V1	csr_rw	adc_ctrl_csr_rw	1.750s	470.818us	20	20	100.00
V1	csr_bit_bash	adc_ctrl_csr_bit_bash	3.344m	39.451ms	5	5	100.00
V1	csr_aliasing	adc_ctrl_csr_aliasing	3.040s	953.762us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	adc_ctrl_csr_mem_rw_with_rand_reset	1.730s	424.659us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	adc_ctrl_csr_rw	1.750s	470.818us	20	20	100.00
		adc_ctrl_csr_aliasing	3.040s	953.762us	5	5	100.00
V1		TOTAL			105	105	100.00
V2	filters_polled	adc_ctrl_filters_polled	18.495m	496.032ms	50	50	100.00
V2	filters_polled_fixed	adc_ctrl_filters_polled_fixed	19.671m	486.062ms	50	50	100.00
V2	filters_interrupt	adc_ctrl_filters_interrupt	19.908m	480.631ms	50	50	100.00
V2	filters_interrupt_fixed	adc_ctrl_filters_interrupt_fixed	19.755m	501.104ms	50	50	100.00
V2	filters_wakeup	adc_ctrl_filters_wakeup	24.058m	703.538ms	50	50	100.00
V2	filters_wakeup_fixed	adc_ctrl_filters_wakeup_fixed	24.334m	616.452ms	50	50	100.00
V2	filters_both	adc_ctrl_filters_both	20.683m	524.321ms	48	50	96.00
V2	clock_gating	adc_ctrl_clock_gating	21.359m	523.022ms	50	50	100.00
V2	poweron_counter	adc_ctrl_poweron_counter	13.590s	5.010ms	50	50	100.00
V2	lowpower_counter	adc_ctrl_lowpower_counter	1.704m	44.169ms	50	50	100.00
V2	fsm_reset	adc_ctrl_fsm_reset	11.479m	122.719ms	50	50	100.00
V2	stress_all	adc_ctrl_stress_all	26.660m	679.006ms	50	50	100.00
V2	alert_test	adc_ctrl_alert_test	1.840s	525.872us	50	50	100.00
V2	intr_test	adc_ctrl_intr_test	1.770s	530.507us	50	50	100.00
V2	tl_d_oob_addr_access	adc_ctrl_tl_errors	3.770s	608.138us	20	20	100.00
V2	tl_d_illegal_access	adc_ctrl_tl_errors	3.770s	608.138us	20	20	100.00
V2	tl_d_outstanding_access	adc_ctrl_csr_hw_reset	3.070s	1.153ms	5	5	100.00
		adc_ctrl_csr_rw	1.750s	470.818us	20	20	100.00
		adc_ctrl_csr_aliasing	3.040s	953.762us	5	5	100.00
		adc_ctrl_same_csr_outstanding	18.330s	4.551ms	20	20	100.00
V2	tl_d_partial_access	adc_ctrl_csr_hw_reset	3.070s	1.153ms	5	5	100.00
		adc_ctrl_csr_rw	1.750s	470.818us	20	20	100.00
		adc_ctrl_csr_aliasing	3.040s	953.762us	5	5	100.00
		adc_ctrl_same_csr_outstanding	18.330s	4.551ms	20	20	100.00
V2		TOTAL			738	740	99.73
V2S	tl_intg_err	adc_ctrl_sec_cm	18.240s	8.146ms	5	5	100.00
		adc_ctrl_tl_intg_err	24.300s	8.682ms	20	20	100.00
V2S	sec_cm_bus_integrity	adc_ctrl_tl_intg_err	24.300s	8.682ms	20	20	100.00
V2S		TOTAL			25	25	100.00
V3	stress_all_with_rand_reset	adc_ctrl_stress_all_with_rand_reset	9.461m	258.332ms	50	50	100.00
V3		TOTAL			50	50	100.00
		TOTAL			918	920	99.78

Testplan Progress

Items	Total	Written	Passing	Progress
V1	6	6	6	100.00
V2	16	16	15	93.75
V2S	2	2	2	100.00
V3	1	1	1	100.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
97.78	99.07	96.67	100.00	100.00	98.83	98.33	91.54

Failure Buckets

UVM_FATAL (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue has 2 failures:
- Test adc_ctrl_filters_both has 2 failures.
  - 5.adc_ctrl_filters_both.32298180770893584705869861799998003796591747333354364102488911070479483436845
    Line 357, in log /container/opentitan-public/scratch/os_regression/adc_ctrl-sim-vcs/5.adc_ctrl_filters_both/latest/run.log
```
  UVM_FATAL @ 600000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 600000000000 ps hit, indicating a probable testbench issue
  UVM_INFO @ 600000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 38.adc_ctrl_filters_both.201593715956981871266999951218487753264607821820797794054136596073329406721
    Line 357, in log /container/opentitan-public/scratch/os_regression/adc_ctrl-sim-vcs/38.adc_ctrl_filters_both/latest/run.log
```
  UVM_FATAL @ 600000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 600000000000 ps hit, indicating a probable testbench issue
  UVM_INFO @ 600000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

ADC_CTRL Simulation Results

Tuesday July 16 2024 23:15:02 UTC

GitHub Revision: aad711e1bc

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 38297581588405771015102977205739484163575733999253050480227719508149669635625

Test Results

Testplan Progress

Coverage Results

Coverage Dashboard

Failure Buckets

Past Results

GitHub Revision: `aad711e1bc`