ADC_CTRL Simulation Results

Wednesday July 17 2024 23:02:16 UTC

GitHub Revision: `8b2da8db5e`

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 31877364624131593519988921539075110140045739991215723614576185349550879231344

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	adc_ctrl_smoke	16.260s	6.021ms	50	50	100.00
V1	csr_hw_reset	adc_ctrl_csr_hw_reset	3.290s	1.151ms	5	5	100.00
V1	csr_rw	adc_ctrl_csr_rw	2.050s	544.723us	20	20	100.00
V1	csr_bit_bash	adc_ctrl_csr_bit_bash	58.100s	17.317ms	5	5	100.00
V1	csr_aliasing	adc_ctrl_csr_aliasing	4.660s	1.081ms	5	5	100.00
V1	csr_mem_rw_with_rand_reset	adc_ctrl_csr_mem_rw_with_rand_reset	2.430s	647.517us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	adc_ctrl_csr_rw	2.050s	544.723us	20	20	100.00
		adc_ctrl_csr_aliasing	4.660s	1.081ms	5	5	100.00
V1		TOTAL			105	105	100.00
V2	filters_polled	adc_ctrl_filters_polled	18.442m	493.165ms	50	50	100.00
V2	filters_polled_fixed	adc_ctrl_filters_polled_fixed	20.346m	492.873ms	50	50	100.00
V2	filters_interrupt	adc_ctrl_filters_interrupt	20.208m	494.954ms	50	50	100.00
V2	filters_interrupt_fixed	adc_ctrl_filters_interrupt_fixed	20.580m	495.590ms	50	50	100.00
V2	filters_wakeup	adc_ctrl_filters_wakeup	24.014m	638.290ms	50	50	100.00
V2	filters_wakeup_fixed	adc_ctrl_filters_wakeup_fixed	23.274m	602.686ms	50	50	100.00
V2	filters_both	adc_ctrl_filters_both	21.967m	558.289ms	50	50	100.00
V2	clock_gating	adc_ctrl_clock_gating	21.671m	619.016ms	50	50	100.00
V2	poweron_counter	adc_ctrl_poweron_counter	13.410s	5.125ms	50	50	100.00
V2	lowpower_counter	adc_ctrl_lowpower_counter	1.871m	46.185ms	50	50	100.00
V2	fsm_reset	adc_ctrl_fsm_reset	12.191m	136.304ms	50	50	100.00
V2	stress_all	adc_ctrl_stress_all	23.939m	464.118ms	50	50	100.00
V2	alert_test	adc_ctrl_alert_test	1.740s	443.059us	50	50	100.00
V2	intr_test	adc_ctrl_intr_test	1.780s	510.130us	50	50	100.00
V2	tl_d_oob_addr_access	adc_ctrl_tl_errors	3.910s	619.045us	20	20	100.00
V2	tl_d_illegal_access	adc_ctrl_tl_errors	3.910s	619.045us	20	20	100.00
V2	tl_d_outstanding_access	adc_ctrl_csr_hw_reset	3.290s	1.151ms	5	5	100.00
		adc_ctrl_csr_rw	2.050s	544.723us	20	20	100.00
		adc_ctrl_csr_aliasing	4.660s	1.081ms	5	5	100.00
		adc_ctrl_same_csr_outstanding	15.520s	4.876ms	20	20	100.00
V2	tl_d_partial_access	adc_ctrl_csr_hw_reset	3.290s	1.151ms	5	5	100.00
		adc_ctrl_csr_rw	2.050s	544.723us	20	20	100.00
		adc_ctrl_csr_aliasing	4.660s	1.081ms	5	5	100.00
		adc_ctrl_same_csr_outstanding	15.520s	4.876ms	20	20	100.00
V2		TOTAL			740	740	100.00
V2S	tl_intg_err	adc_ctrl_sec_cm	10.590s	4.131ms	5	5	100.00
		adc_ctrl_tl_intg_err	20.340s	8.438ms	20	20	100.00
V2S	sec_cm_bus_integrity	adc_ctrl_tl_intg_err	20.340s	8.438ms	20	20	100.00
V2S		TOTAL			25	25	100.00
V3	stress_all_with_rand_reset	adc_ctrl_stress_all_with_rand_reset	9.001m	356.103ms	49	50	98.00
V3		TOTAL			49	50	98.00
		TOTAL			919	920	99.89

Testplan Progress

Items	Total	Written	Passing	Progress
V1	6	6	6	100.00
V2	16	16	16	100.00
V2S	2	2	2	100.00
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
97.75	99.07	96.67	100.00	100.00	98.83	98.33	91.34

Failure Buckets

UVM_ERROR (adc_ctrl_scoreboard.sv:137) [scoreboard] Check failed m_wakeup == m_expected_wakeup (* [*] vs * [*]) has 1 failures:
- Test adc_ctrl_stress_all_with_rand_reset has 1 failures.
  - 15.adc_ctrl_stress_all_with_rand_reset.114770126566634987298053101976065050970253502501243785012080559435380485949326
    Line 444, in log /container/opentitan-public/scratch/os_regression/adc_ctrl-sim-vcs/15.adc_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 267818388499 ps: (adc_ctrl_scoreboard.sv:137) [uvm_test_top.env.scoreboard] Check failed m_wakeup == m_expected_wakeup (1 [0x1] vs 0 [0x0])
  UVM_INFO @ 267818388499 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

ADC_CTRL Simulation Results

Wednesday July 17 2024 23:02:16 UTC

GitHub Revision: 8b2da8db5e

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 31877364624131593519988921539075110140045739991215723614576185349550879231344

Test Results

Testplan Progress

Coverage Results

Coverage Dashboard

Failure Buckets

Past Results

GitHub Revision: `8b2da8db5e`