ADC_CTRL Simulation Results

Thursday July 18 2024 23:02:12 UTC

GitHub Revision: 974aaab627

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 46057207235241274571178436692064798722168129065126426307050395083305588858879

Test Results

Stage Name Tests Max Job Runtime Simulated Time Passing Total Pass Rate
V1 smoke adc_ctrl_smoke 15.390s 5.746ms 50 50 100.00
V1 csr_hw_reset adc_ctrl_csr_hw_reset 2.200s 644.134us 5 5 100.00
V1 csr_rw adc_ctrl_csr_rw 2.050s 498.135us 20 20 100.00
V1 csr_bit_bash adc_ctrl_csr_bit_bash 1.606m 23.501ms 5 5 100.00
V1 csr_aliasing adc_ctrl_csr_aliasing 6.040s 1.317ms 5 5 100.00
V1 csr_mem_rw_with_rand_reset adc_ctrl_csr_mem_rw_with_rand_reset 2.180s 526.826us 20 20 100.00
V1 regwen_csr_and_corresponding_lockable_csr adc_ctrl_csr_rw 2.050s 498.135us 20 20 100.00
adc_ctrl_csr_aliasing 6.040s 1.317ms 5 5 100.00
V1 TOTAL 105 105 100.00
V2 filters_polled adc_ctrl_filters_polled 18.660m 496.688ms 50 50 100.00
V2 filters_polled_fixed adc_ctrl_filters_polled_fixed 19.558m 489.303ms 50 50 100.00
V2 filters_interrupt adc_ctrl_filters_interrupt 19.142m 486.249ms 50 50 100.00
V2 filters_interrupt_fixed adc_ctrl_filters_interrupt_fixed 20.247m 496.617ms 50 50 100.00
V2 filters_wakeup adc_ctrl_filters_wakeup 23.993m 615.156ms 50 50 100.00
V2 filters_wakeup_fixed adc_ctrl_filters_wakeup_fixed 25.150m 602.963ms 50 50 100.00
V2 filters_both adc_ctrl_filters_both 22.851m 598.316ms 50 50 100.00
V2 clock_gating adc_ctrl_clock_gating 20.097m 507.670ms 50 50 100.00
V2 poweron_counter adc_ctrl_poweron_counter 13.130s 5.334ms 50 50 100.00
V2 lowpower_counter adc_ctrl_lowpower_counter 1.649m 42.747ms 50 50 100.00
V2 fsm_reset adc_ctrl_fsm_reset 12.304m 126.446ms 50 50 100.00
V2 stress_all adc_ctrl_stress_all 31.870m 752.445ms 50 50 100.00
V2 alert_test adc_ctrl_alert_test 1.870s 526.371us 50 50 100.00
V2 intr_test adc_ctrl_intr_test 1.830s 529.877us 50 50 100.00
V2 tl_d_oob_addr_access adc_ctrl_tl_errors 3.300s 514.580us 20 20 100.00
V2 tl_d_illegal_access adc_ctrl_tl_errors 3.300s 514.580us 20 20 100.00
V2 tl_d_outstanding_access adc_ctrl_csr_hw_reset 2.200s 644.134us 5 5 100.00
adc_ctrl_csr_rw 2.050s 498.135us 20 20 100.00
adc_ctrl_csr_aliasing 6.040s 1.317ms 5 5 100.00
adc_ctrl_same_csr_outstanding 14.980s 5.223ms 20 20 100.00
V2 tl_d_partial_access adc_ctrl_csr_hw_reset 2.200s 644.134us 5 5 100.00
adc_ctrl_csr_rw 2.050s 498.135us 20 20 100.00
adc_ctrl_csr_aliasing 6.040s 1.317ms 5 5 100.00
adc_ctrl_same_csr_outstanding 14.980s 5.223ms 20 20 100.00
V2 TOTAL 740 740 100.00
V2S tl_intg_err adc_ctrl_sec_cm 21.890s 8.600ms 5 5 100.00
adc_ctrl_tl_intg_err 23.100s 8.988ms 20 20 100.00
V2S sec_cm_bus_integrity adc_ctrl_tl_intg_err 23.100s 8.988ms 20 20 100.00
V2S TOTAL 25 25 100.00
V3 stress_all_with_rand_reset adc_ctrl_stress_all_with_rand_reset 11.128m 1.437s 50 50 100.00
V3 TOTAL 50 50 100.00
TOTAL 920 920 100.00

Testplan Progress

Items Total Written Passing Progress
V1 6 6 6 100.00
V2 16 16 16 100.00
V2S 2 2 2 100.00
V3 1 1 1 100.00

Coverage Results

Coverage Dashboard

SCORE LINE COND TOGGLE FSM BRANCH ASSERT GROUP
97.69 99.07 96.67 100.00 100.00 98.83 98.33 90.94

Past Results