ADC_CTRL Simulation Results

Friday July 19 2024 23:02:26 UTC

GitHub Revision: e971cd9798

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 26138077499038500271813583950138268511494909685260487774440110801232111361107

Test Results

Stage Name Tests Max Job Runtime Simulated Time Passing Total Pass Rate
V1 smoke adc_ctrl_smoke 17.850s 6.066ms 50 50 100.00
V1 csr_hw_reset adc_ctrl_csr_hw_reset 3.620s 1.210ms 5 5 100.00
V1 csr_rw adc_ctrl_csr_rw 2.130s 578.066us 20 20 100.00
V1 csr_bit_bash adc_ctrl_csr_bit_bash 3.427m 51.858ms 5 5 100.00
V1 csr_aliasing adc_ctrl_csr_aliasing 3.600s 980.243us 5 5 100.00
V1 csr_mem_rw_with_rand_reset adc_ctrl_csr_mem_rw_with_rand_reset 2.450s 652.232us 20 20 100.00
V1 regwen_csr_and_corresponding_lockable_csr adc_ctrl_csr_rw 2.130s 578.066us 20 20 100.00
adc_ctrl_csr_aliasing 3.600s 980.243us 5 5 100.00
V1 TOTAL 105 105 100.00
V2 filters_polled adc_ctrl_filters_polled 19.416m 494.110ms 50 50 100.00
V2 filters_polled_fixed adc_ctrl_filters_polled_fixed 19.934m 489.212ms 50 50 100.00
V2 filters_interrupt adc_ctrl_filters_interrupt 20.075m 491.720ms 50 50 100.00
V2 filters_interrupt_fixed adc_ctrl_filters_interrupt_fixed 21.777m 499.341ms 50 50 100.00
V2 filters_wakeup adc_ctrl_filters_wakeup 25.892m 616.948ms 50 50 100.00
V2 filters_wakeup_fixed adc_ctrl_filters_wakeup_fixed 25.191m 625.471ms 50 50 100.00
V2 filters_both adc_ctrl_filters_both 22.196m 564.048ms 50 50 100.00
V2 clock_gating adc_ctrl_clock_gating 20.003m 540.658ms 50 50 100.00
V2 poweron_counter adc_ctrl_poweron_counter 13.020s 5.194ms 50 50 100.00
V2 lowpower_counter adc_ctrl_lowpower_counter 2.002m 48.157ms 50 50 100.00
V2 fsm_reset adc_ctrl_fsm_reset 11.809m 128.428ms 50 50 100.00
V2 stress_all adc_ctrl_stress_all 30.914m 620.041ms 50 50 100.00
V2 alert_test adc_ctrl_alert_test 1.930s 525.489us 50 50 100.00
V2 intr_test adc_ctrl_intr_test 1.890s 521.477us 50 50 100.00
V2 tl_d_oob_addr_access adc_ctrl_tl_errors 3.770s 626.811us 20 20 100.00
V2 tl_d_illegal_access adc_ctrl_tl_errors 3.770s 626.811us 20 20 100.00
V2 tl_d_outstanding_access adc_ctrl_csr_hw_reset 3.620s 1.210ms 5 5 100.00
adc_ctrl_csr_rw 2.130s 578.066us 20 20 100.00
adc_ctrl_csr_aliasing 3.600s 980.243us 5 5 100.00
adc_ctrl_same_csr_outstanding 12.530s 2.672ms 20 20 100.00
V2 tl_d_partial_access adc_ctrl_csr_hw_reset 3.620s 1.210ms 5 5 100.00
adc_ctrl_csr_rw 2.130s 578.066us 20 20 100.00
adc_ctrl_csr_aliasing 3.600s 980.243us 5 5 100.00
adc_ctrl_same_csr_outstanding 12.530s 2.672ms 20 20 100.00
V2 TOTAL 740 740 100.00
V2S tl_intg_err adc_ctrl_sec_cm 20.970s 8.003ms 5 5 100.00
adc_ctrl_tl_intg_err 22.200s 8.017ms 20 20 100.00
V2S sec_cm_bus_integrity adc_ctrl_tl_intg_err 22.200s 8.017ms 20 20 100.00
V2S TOTAL 25 25 100.00
V3 stress_all_with_rand_reset adc_ctrl_stress_all_with_rand_reset 22.402m 1.654s 50 50 100.00
V3 TOTAL 50 50 100.00
TOTAL 920 920 100.00

Testplan Progress

Items Total Written Passing Progress
V1 6 6 6 100.00
V2 16 16 16 100.00
V2S 2 2 2 100.00
V3 1 1 1 100.00

Coverage Results

Coverage Dashboard

SCORE LINE COND TOGGLE FSM BRANCH ASSERT GROUP
97.75 99.07 96.67 100.00 100.00 98.83 98.33 91.37

Past Results