ADC_CTRL Simulation Results

Thursday August 01 2024 23:02:20 UTC

GitHub Revision: `625f353e9c`

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 85273092133191575795496895645039765542965103003083525273509664765586668778052

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	adc_ctrl_smoke	15.790s	5.871ms	50	50	100.00
V1	csr_hw_reset	adc_ctrl_csr_hw_reset	3.450s	1.186ms	5	5	100.00
V1	csr_rw	adc_ctrl_csr_rw	2.000s	545.596us	20	20	100.00
V1	csr_bit_bash	adc_ctrl_csr_bit_bash	1.021m	53.244ms	5	5	100.00
V1	csr_aliasing	adc_ctrl_csr_aliasing	4.650s	1.185ms	5	5	100.00
V1	csr_mem_rw_with_rand_reset	adc_ctrl_csr_mem_rw_with_rand_reset	2.380s	547.276us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	adc_ctrl_csr_rw	2.000s	545.596us	20	20	100.00
		adc_ctrl_csr_aliasing	4.650s	1.185ms	5	5	100.00
V1		TOTAL			105	105	100.00
V2	filters_polled	adc_ctrl_filters_polled	20.015m	484.372ms	50	50	100.00
V2	filters_polled_fixed	adc_ctrl_filters_polled_fixed	19.941m	492.979ms	50	50	100.00
V2	filters_interrupt	adc_ctrl_filters_interrupt	19.339m	481.558ms	50	50	100.00
V2	filters_interrupt_fixed	adc_ctrl_filters_interrupt_fixed	20.059m	498.661ms	50	50	100.00
V2	filters_wakeup	adc_ctrl_filters_wakeup	21.260m	529.806ms	50	50	100.00
V2	filters_wakeup_fixed	adc_ctrl_filters_wakeup_fixed	23.734m	595.539ms	50	50	100.00
V2	filters_both	adc_ctrl_filters_both	21.587m	536.987ms	49	50	98.00
V2	clock_gating	adc_ctrl_clock_gating	19.535m	536.695ms	50	50	100.00
V2	poweron_counter	adc_ctrl_poweron_counter	12.470s	5.160ms	50	50	100.00
V2	lowpower_counter	adc_ctrl_lowpower_counter	1.728m	47.717ms	50	50	100.00
V2	fsm_reset	adc_ctrl_fsm_reset	11.954m	133.723ms	50	50	100.00
V2	stress_all	adc_ctrl_stress_all	26.719m	652.848ms	50	50	100.00
V2	alert_test	adc_ctrl_alert_test	1.850s	527.294us	50	50	100.00
V2	intr_test	adc_ctrl_intr_test	1.910s	513.827us	50	50	100.00
V2	tl_d_oob_addr_access	adc_ctrl_tl_errors	3.270s	522.498us	20	20	100.00
V2	tl_d_illegal_access	adc_ctrl_tl_errors	3.270s	522.498us	20	20	100.00
V2	tl_d_outstanding_access	adc_ctrl_csr_hw_reset	3.450s	1.186ms	5	5	100.00
		adc_ctrl_csr_rw	2.000s	545.596us	20	20	100.00
		adc_ctrl_csr_aliasing	4.650s	1.185ms	5	5	100.00
		adc_ctrl_same_csr_outstanding	18.320s	4.936ms	20	20	100.00
V2	tl_d_partial_access	adc_ctrl_csr_hw_reset	3.450s	1.186ms	5	5	100.00
		adc_ctrl_csr_rw	2.000s	545.596us	20	20	100.00
		adc_ctrl_csr_aliasing	4.650s	1.185ms	5	5	100.00
		adc_ctrl_same_csr_outstanding	18.320s	4.936ms	20	20	100.00
V2		TOTAL			739	740	99.86
V2S	tl_intg_err	adc_ctrl_sec_cm	16.570s	7.975ms	5	5	100.00
		adc_ctrl_tl_intg_err	20.180s	7.273ms	20	20	100.00
V2S	sec_cm_bus_integrity	adc_ctrl_tl_intg_err	20.180s	7.273ms	20	20	100.00
V2S		TOTAL			25	25	100.00
V3	stress_all_with_rand_reset	adc_ctrl_stress_all_with_rand_reset	17.711m	874.550ms	49	50	98.00
V3		TOTAL			49	50	98.00
		TOTAL			918	920	99.78

Testplan Progress

Items	Total	Written	Passing	Progress
V1	6	6	6	100.00
V2	16	16	15	93.75
V2S	2	2	2	100.00
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
97.74	99.07	96.67	100.00	100.00	98.83	98.33	91.27

Failure Buckets

UVM_FATAL (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue has 1 failures:
- Test adc_ctrl_filters_both has 1 failures.
  - 4.adc_ctrl_filters_both.1717479296284072361924350756263938796699848849110022618783119707532532631630
    Line 357, in log /container/opentitan-public/scratch/os_regression/adc_ctrl-sim-vcs/4.adc_ctrl_filters_both/latest/run.log
```
  UVM_FATAL @ 600000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 600000000000 ps hit, indicating a probable testbench issue
  UVM_INFO @ 600000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (adc_ctrl_scoreboard.sv:137) [scoreboard] Check failed m_wakeup == m_expected_wakeup (* [*] vs * [*]) has 1 failures:
- Test adc_ctrl_stress_all_with_rand_reset has 1 failures.
  - 27.adc_ctrl_stress_all_with_rand_reset.41113735516523636197245501808220467322573579479141745064760854882265860232157
    Line 366, in log /container/opentitan-public/scratch/os_regression/adc_ctrl-sim-vcs/27.adc_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 66558714890 ps: (adc_ctrl_scoreboard.sv:137) [uvm_test_top.env.scoreboard] Check failed m_wakeup == m_expected_wakeup (1 [0x1] vs 0 [0x0])
  UVM_INFO @ 66558714890 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

ADC_CTRL Simulation Results

Thursday August 01 2024 23:02:20 UTC

GitHub Revision: 625f353e9c

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 85273092133191575795496895645039765542965103003083525273509664765586668778052

Test Results

Testplan Progress

Coverage Results

Coverage Dashboard

Failure Buckets

Past Results

GitHub Revision: `625f353e9c`