ADC_CTRL Simulation Results

Friday August 02 2024 23:02:48 UTC

GitHub Revision: c8985d6745

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 75989420798843487383163268541581889763599806834398027919895759109584083292465

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	adc_ctrl_smoke	16.020s	5.800ms	50	50	100.00
V1	csr_hw_reset	adc_ctrl_csr_hw_reset	2.890s	916.501us	5	5	100.00
V1	csr_rw	adc_ctrl_csr_rw	1.940s	444.619us	20	20	100.00
V1	csr_bit_bash	adc_ctrl_csr_bit_bash	1.414m	26.378ms	5	5	100.00
V1	csr_aliasing	adc_ctrl_csr_aliasing	6.850s	1.142ms	5	5	100.00
V1	csr_mem_rw_with_rand_reset	adc_ctrl_csr_mem_rw_with_rand_reset	2.280s	571.415us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	adc_ctrl_csr_rw	1.940s	444.619us	20	20	100.00
		adc_ctrl_csr_aliasing	6.850s	1.142ms	5	5	100.00
V1		TOTAL			105	105	100.00
V2	filters_polled	adc_ctrl_filters_polled	19.676m	495.684ms	50	50	100.00
V2	filters_polled_fixed	adc_ctrl_filters_polled_fixed	18.819m	493.482ms	50	50	100.00
V2	filters_interrupt	adc_ctrl_filters_interrupt	20.356m	503.483ms	50	50	100.00
V2	filters_interrupt_fixed	adc_ctrl_filters_interrupt_fixed	19.704m	492.995ms	50	50	100.00
V2	filters_wakeup	adc_ctrl_filters_wakeup	23.033m	631.799ms	50	50	100.00
V2	filters_wakeup_fixed	adc_ctrl_filters_wakeup_fixed	22.412m	583.866ms	50	50	100.00
V2	filters_both	adc_ctrl_filters_both	22.318m	572.453ms	50	50	100.00
V2	clock_gating	adc_ctrl_clock_gating	21.101m	571.456ms	50	50	100.00
V2	poweron_counter	adc_ctrl_poweron_counter	13.990s	5.507ms	50	50	100.00
V2	lowpower_counter	adc_ctrl_lowpower_counter	1.750m	42.859ms	50	50	100.00
V2	fsm_reset	adc_ctrl_fsm_reset	11.669m	139.408ms	50	50	100.00
V2	stress_all	adc_ctrl_stress_all	28.475m	545.504ms	50	50	100.00
V2	alert_test	adc_ctrl_alert_test	1.760s	510.707us	50	50	100.00
V2	intr_test	adc_ctrl_intr_test	1.810s	530.766us	50	50	100.00
V2	tl_d_oob_addr_access	adc_ctrl_tl_errors	3.570s	645.706us	20	20	100.00
V2	tl_d_illegal_access	adc_ctrl_tl_errors	3.570s	645.706us	20	20	100.00
V2	tl_d_outstanding_access	adc_ctrl_csr_hw_reset	2.890s	916.501us	5	5	100.00
		adc_ctrl_csr_rw	1.940s	444.619us	20	20	100.00
		adc_ctrl_csr_aliasing	6.850s	1.142ms	5	5	100.00
		adc_ctrl_same_csr_outstanding	17.420s	5.104ms	20	20	100.00
V2	tl_d_partial_access	adc_ctrl_csr_hw_reset	2.890s	916.501us	5	5	100.00
		adc_ctrl_csr_rw	1.940s	444.619us	20	20	100.00
		adc_ctrl_csr_aliasing	6.850s	1.142ms	5	5	100.00
		adc_ctrl_same_csr_outstanding	17.420s	5.104ms	20	20	100.00
V2		TOTAL			740	740	100.00
V2S	tl_intg_err	adc_ctrl_sec_cm	9.290s	8.000ms	5	5	100.00
		adc_ctrl_tl_intg_err	23.800s	9.322ms	20	20	100.00
V2S	sec_cm_bus_integrity	adc_ctrl_tl_intg_err	23.800s	9.322ms	20	20	100.00
V2S		TOTAL			25	25	100.00
V3	stress_all_with_rand_reset	adc_ctrl_stress_all_with_rand_reset	17.243m	510.739ms	49	50	98.00
V3		TOTAL			49	50	98.00
		TOTAL			919	920	99.89

Testplan Progress

Items	Total	Written	Passing	Progress
V1	6	6	6	100.00
V2	16	16	16	100.00
V2S	2	2	2	100.00
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
97.73	99.07	96.67	100.00	100.00	98.83	98.33	91.19

Failure Buckets

• Offending '(np_sample_cnt_q == '0)' has 1 failures:
  • Test adc_ctrl_stress_all_with_rand_reset has 1 failures.

    • 49.adc_ctrl_stress_all_with_rand_reset.14052847552816016777593882849861608752249849889283064104639991610336277437344
      Line 408, in log /container/opentitan-public/scratch/os_regression/adc_ctrl-sim-vcs/49.adc_ctrl_stress_all_with_rand_reset/latest/run.log

            Offending '(np_sample_cnt_q == '0)'
        UVM_ERROR @ 1010146276574 ps: (adc_ctrl_fsm.sv:384) [ASSERT FAILED] NpCntClrPwrDn_A
        UVM_INFO @ 1010146276574 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

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