ADC_CTRL Simulation Results

Saturday August 03 2024 23:02:32 UTC

GitHub Revision: `c8985d6745`

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 108668412464624965510474525856307009670790505545344576298908689226672042444441

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	adc_ctrl_smoke	15.290s	5.740ms	50	50	100.00
V1	csr_hw_reset	adc_ctrl_csr_hw_reset	3.400s	1.284ms	5	5	100.00
V1	csr_rw	adc_ctrl_csr_rw	1.770s	461.056us	20	20	100.00
V1	csr_bit_bash	adc_ctrl_csr_bit_bash	47.040s	9.130ms	5	5	100.00
V1	csr_aliasing	adc_ctrl_csr_aliasing	4.150s	1.032ms	5	5	100.00
V1	csr_mem_rw_with_rand_reset	adc_ctrl_csr_mem_rw_with_rand_reset	2.090s	422.567us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	adc_ctrl_csr_rw	1.770s	461.056us	20	20	100.00
		adc_ctrl_csr_aliasing	4.150s	1.032ms	5	5	100.00
V1		TOTAL			105	105	100.00
V2	filters_polled	adc_ctrl_filters_polled	20.205m	496.602ms	50	50	100.00
V2	filters_polled_fixed	adc_ctrl_filters_polled_fixed	20.536m	502.754ms	50	50	100.00
V2	filters_interrupt	adc_ctrl_filters_interrupt	19.438m	488.974ms	50	50	100.00
V2	filters_interrupt_fixed	adc_ctrl_filters_interrupt_fixed	20.563m	499.891ms	50	50	100.00
V2	filters_wakeup	adc_ctrl_filters_wakeup	24.407m	619.708ms	50	50	100.00
V2	filters_wakeup_fixed	adc_ctrl_filters_wakeup_fixed	23.479m	601.207ms	50	50	100.00
V2	filters_both	adc_ctrl_filters_both	21.684m	525.566ms	50	50	100.00
V2	clock_gating	adc_ctrl_clock_gating	18.954m	491.675ms	50	50	100.00
V2	poweron_counter	adc_ctrl_poweron_counter	12.810s	4.882ms	50	50	100.00
V2	lowpower_counter	adc_ctrl_lowpower_counter	1.747m	42.600ms	50	50	100.00
V2	fsm_reset	adc_ctrl_fsm_reset	12.646m	143.654ms	50	50	100.00
V2	stress_all	adc_ctrl_stress_all	29.791m	739.167ms	50	50	100.00
V2	alert_test	adc_ctrl_alert_test	1.760s	499.254us	50	50	100.00
V2	intr_test	adc_ctrl_intr_test	1.970s	530.749us	50	50	100.00
V2	tl_d_oob_addr_access	adc_ctrl_tl_errors	3.570s	515.918us	20	20	100.00
V2	tl_d_illegal_access	adc_ctrl_tl_errors	3.570s	515.918us	20	20	100.00
V2	tl_d_outstanding_access	adc_ctrl_csr_hw_reset	3.400s	1.284ms	5	5	100.00
		adc_ctrl_csr_rw	1.770s	461.056us	20	20	100.00
		adc_ctrl_csr_aliasing	4.150s	1.032ms	5	5	100.00
		adc_ctrl_same_csr_outstanding	16.530s	5.075ms	20	20	100.00
V2	tl_d_partial_access	adc_ctrl_csr_hw_reset	3.400s	1.284ms	5	5	100.00
		adc_ctrl_csr_rw	1.770s	461.056us	20	20	100.00
		adc_ctrl_csr_aliasing	4.150s	1.032ms	5	5	100.00
		adc_ctrl_same_csr_outstanding	16.530s	5.075ms	20	20	100.00
V2		TOTAL			740	740	100.00
V2S	tl_intg_err	adc_ctrl_sec_cm	6.040s	4.355ms	5	5	100.00
		adc_ctrl_tl_intg_err	23.440s	8.767ms	20	20	100.00
V2S	sec_cm_bus_integrity	adc_ctrl_tl_intg_err	23.440s	8.767ms	20	20	100.00
V2S		TOTAL			25	25	100.00
V3	stress_all_with_rand_reset	adc_ctrl_stress_all_with_rand_reset	8.358m	1.134s	49	50	98.00
V3		TOTAL			49	50	98.00
		TOTAL			919	920	99.89

Testplan Progress

Items	Total	Written	Passing	Progress
V1	6	6	6	100.00
V2	16	16	16	100.00
V2S	2	2	2	100.00
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
97.69	99.07	96.67	100.00	100.00	98.83	98.33	90.92

Failure Buckets

UVM_ERROR (adc_ctrl_scoreboard.sv:137) [scoreboard] Check failed m_wakeup == m_expected_wakeup (* [*] vs * [*]) has 1 failures:
- Test adc_ctrl_stress_all_with_rand_reset has 1 failures.
  - 18.adc_ctrl_stress_all_with_rand_reset.70778853672819926792843008882393983062942088929348822951901945269443836196376
    Line 353, in log /container/opentitan-public/scratch/os_regression/adc_ctrl-sim-vcs/18.adc_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 10203684986 ps: (adc_ctrl_scoreboard.sv:137) [uvm_test_top.env.scoreboard] Check failed m_wakeup == m_expected_wakeup (1 [0x1] vs 0 [0x0])
  UVM_INFO @ 10203684986 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

ADC_CTRL Simulation Results

Saturday August 03 2024 23:02:32 UTC

GitHub Revision: c8985d6745

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 108668412464624965510474525856307009670790505545344576298908689226672042444441

Test Results

Testplan Progress

Coverage Results

Coverage Dashboard

Failure Buckets

Past Results

GitHub Revision: `c8985d6745`