ADC_CTRL Simulation Results

Sunday August 04 2024 23:02:21 UTC

GitHub Revision: `c8985d6745`

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 107130591329296133632864610148388701578652631018704528920799220771546870921898

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	adc_ctrl_smoke	16.480s	6.057ms	50	50	100.00
V1	csr_hw_reset	adc_ctrl_csr_hw_reset	2.390s	760.244us	5	5	100.00
V1	csr_rw	adc_ctrl_csr_rw	1.970s	447.112us	20	20	100.00
V1	csr_bit_bash	adc_ctrl_csr_bit_bash	1.101m	26.015ms	5	5	100.00
V1	csr_aliasing	adc_ctrl_csr_aliasing	4.770s	1.090ms	5	5	100.00
V1	csr_mem_rw_with_rand_reset	adc_ctrl_csr_mem_rw_with_rand_reset	2.150s	476.073us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	adc_ctrl_csr_rw	1.970s	447.112us	20	20	100.00
		adc_ctrl_csr_aliasing	4.770s	1.090ms	5	5	100.00
V1		TOTAL			105	105	100.00
V2	filters_polled	adc_ctrl_filters_polled	20.584m	494.991ms	50	50	100.00
V2	filters_polled_fixed	adc_ctrl_filters_polled_fixed	18.779m	493.053ms	50	50	100.00
V2	filters_interrupt	adc_ctrl_filters_interrupt	20.197m	489.549ms	50	50	100.00
V2	filters_interrupt_fixed	adc_ctrl_filters_interrupt_fixed	19.281m	497.712ms	50	50	100.00
V2	filters_wakeup	adc_ctrl_filters_wakeup	24.778m	624.459ms	50	50	100.00
V2	filters_wakeup_fixed	adc_ctrl_filters_wakeup_fixed	26.067m	643.859ms	50	50	100.00
V2	filters_both	adc_ctrl_filters_both	22.894m	559.027ms	50	50	100.00
V2	clock_gating	adc_ctrl_clock_gating	22.365m	657.326ms	50	50	100.00
V2	poweron_counter	adc_ctrl_poweron_counter	12.520s	4.854ms	50	50	100.00
V2	lowpower_counter	adc_ctrl_lowpower_counter	1.920m	45.574ms	50	50	100.00
V2	fsm_reset	adc_ctrl_fsm_reset	11.002m	122.915ms	50	50	100.00
V2	stress_all	adc_ctrl_stress_all	53.843m	1.224s	50	50	100.00
V2	alert_test	adc_ctrl_alert_test	1.790s	533.146us	50	50	100.00
V2	intr_test	adc_ctrl_intr_test	1.830s	530.796us	50	50	100.00
V2	tl_d_oob_addr_access	adc_ctrl_tl_errors	3.860s	647.446us	20	20	100.00
V2	tl_d_illegal_access	adc_ctrl_tl_errors	3.860s	647.446us	20	20	100.00
V2	tl_d_outstanding_access	adc_ctrl_csr_hw_reset	2.390s	760.244us	5	5	100.00
		adc_ctrl_csr_rw	1.970s	447.112us	20	20	100.00
		adc_ctrl_csr_aliasing	4.770s	1.090ms	5	5	100.00
		adc_ctrl_same_csr_outstanding	21.630s	4.330ms	20	20	100.00
V2	tl_d_partial_access	adc_ctrl_csr_hw_reset	2.390s	760.244us	5	5	100.00
		adc_ctrl_csr_rw	1.970s	447.112us	20	20	100.00
		adc_ctrl_csr_aliasing	4.770s	1.090ms	5	5	100.00
		adc_ctrl_same_csr_outstanding	21.630s	4.330ms	20	20	100.00
V2		TOTAL			740	740	100.00
V2S	tl_intg_err	adc_ctrl_sec_cm	18.080s	8.166ms	5	5	100.00
		adc_ctrl_tl_intg_err	22.520s	8.483ms	20	20	100.00
V2S	sec_cm_bus_integrity	adc_ctrl_tl_intg_err	22.520s	8.483ms	20	20	100.00
V2S		TOTAL			25	25	100.00
V3	stress_all_with_rand_reset	adc_ctrl_stress_all_with_rand_reset	15.321m	973.600ms	48	50	96.00
V3		TOTAL			48	50	96.00
		TOTAL			918	920	99.78

Testplan Progress

Items	Total	Written	Passing	Progress
V1	6	6	6	100.00
V2	16	16	16	100.00
V2S	2	2	2	100.00
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
97.73	99.07	96.67	100.00	100.00	98.83	98.33	91.22

Failure Buckets

UVM_ERROR (adc_ctrl_scoreboard.sv:137) [scoreboard] Check failed m_wakeup == m_expected_wakeup (* [*] vs * [*]) has 1 failures:
- Test adc_ctrl_stress_all_with_rand_reset has 1 failures.
  - 25.adc_ctrl_stress_all_with_rand_reset.78413524154890553328446821745453464539779788352406586119942948472679126027506
    Line 409, in log /container/opentitan-public/scratch/os_regression/adc_ctrl-sim-vcs/25.adc_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 41195239246 ps: (adc_ctrl_scoreboard.sv:137) [uvm_test_top.env.scoreboard] Check failed m_wakeup == m_expected_wakeup (1 [0x1] vs 0 [0x0])
  UVM_INFO @ 41195239246 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (adc_ctrl_scoreboard.sv:405) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) reg name: adc_ctrl_reg_block.filter_status has 1 failures:
- Test adc_ctrl_stress_all_with_rand_reset has 1 failures.
  - 26.adc_ctrl_stress_all_with_rand_reset.15914830270137364226682268634821541797256144627669830184708077986642755827316
    Line 403, in log /container/opentitan-public/scratch/os_regression/adc_ctrl-sim-vcs/26.adc_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 751007297250 ps: (adc_ctrl_scoreboard.sv:405) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (0 [0x0] vs 256 [0x100]) reg name: adc_ctrl_reg_block.filter_status
  UVM_INFO @ 751007297250 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

ADC_CTRL Simulation Results

Sunday August 04 2024 23:02:21 UTC

GitHub Revision: c8985d6745

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 107130591329296133632864610148388701578652631018704528920799220771546870921898

Test Results

Testplan Progress

Coverage Results

Coverage Dashboard

Failure Buckets

Past Results

GitHub Revision: `c8985d6745`