ADC_CTRL Simulation Results

Monday August 05 2024 23:02:13 UTC

GitHub Revision: e4c5daa580

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 57478527486894479494471273459769404654835266620222125964939301612221385668501

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	adc_ctrl_smoke	15.290s	5.896ms	50	50	100.00
V1	csr_hw_reset	adc_ctrl_csr_hw_reset	3.070s	1.053ms	5	5	100.00
V1	csr_rw	adc_ctrl_csr_rw	2.160s	528.481us	20	20	100.00
V1	csr_bit_bash	adc_ctrl_csr_bit_bash	2.964m	51.767ms	5	5	100.00
V1	csr_aliasing	adc_ctrl_csr_aliasing	4.200s	910.755us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	adc_ctrl_csr_mem_rw_with_rand_reset	2.280s	551.082us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	adc_ctrl_csr_rw	2.160s	528.481us	20	20	100.00
		adc_ctrl_csr_aliasing	4.200s	910.755us	5	5	100.00
V1		TOTAL			105	105	100.00
V2	filters_polled	adc_ctrl_filters_polled	20.198m	494.424ms	50	50	100.00
V2	filters_polled_fixed	adc_ctrl_filters_polled_fixed	19.645m	493.448ms	50	50	100.00
V2	filters_interrupt	adc_ctrl_filters_interrupt	19.266m	497.892ms	50	50	100.00
V2	filters_interrupt_fixed	adc_ctrl_filters_interrupt_fixed	19.928m	489.958ms	50	50	100.00
V2	filters_wakeup	adc_ctrl_filters_wakeup	23.310m	598.996ms	50	50	100.00
V2	filters_wakeup_fixed	adc_ctrl_filters_wakeup_fixed	23.957m	598.201ms	50	50	100.00
V2	filters_both	adc_ctrl_filters_both	23.177m	600.000ms	47	50	94.00
V2	clock_gating	adc_ctrl_clock_gating	20.053m	511.658ms	50	50	100.00
V2	poweron_counter	adc_ctrl_poweron_counter	13.460s	5.230ms	50	50	100.00
V2	lowpower_counter	adc_ctrl_lowpower_counter	1.791m	44.681ms	50	50	100.00
V2	fsm_reset	adc_ctrl_fsm_reset	12.377m	144.170ms	50	50	100.00
V2	stress_all	adc_ctrl_stress_all	33.665m	1.563s	50	50	100.00
V2	alert_test	adc_ctrl_alert_test	1.830s	515.632us	50	50	100.00
V2	intr_test	adc_ctrl_intr_test	1.810s	494.426us	50	50	100.00
V2	tl_d_oob_addr_access	adc_ctrl_tl_errors	4.180s	637.038us	20	20	100.00
V2	tl_d_illegal_access	adc_ctrl_tl_errors	4.180s	637.038us	20	20	100.00
V2	tl_d_outstanding_access	adc_ctrl_csr_hw_reset	3.070s	1.053ms	5	5	100.00
		adc_ctrl_csr_rw	2.160s	528.481us	20	20	100.00
		adc_ctrl_csr_aliasing	4.200s	910.755us	5	5	100.00
		adc_ctrl_same_csr_outstanding	19.660s	4.848ms	19	20	95.00
V2	tl_d_partial_access	adc_ctrl_csr_hw_reset	3.070s	1.053ms	5	5	100.00
		adc_ctrl_csr_rw	2.160s	528.481us	20	20	100.00
		adc_ctrl_csr_aliasing	4.200s	910.755us	5	5	100.00
		adc_ctrl_same_csr_outstanding	19.660s	4.848ms	19	20	95.00
V2		TOTAL			736	740	99.46
V2S	tl_intg_err	adc_ctrl_sec_cm	21.760s	8.727ms	5	5	100.00
		adc_ctrl_tl_intg_err	23.400s	8.817ms	20	20	100.00
V2S	sec_cm_bus_integrity	adc_ctrl_tl_intg_err	23.400s	8.817ms	20	20	100.00
V2S		TOTAL			25	25	100.00
V3	stress_all_with_rand_reset	adc_ctrl_stress_all_with_rand_reset	11.060m	497.154ms	50	50	100.00
V3		TOTAL			50	50	100.00
		TOTAL			916	920	99.57

Testplan Progress

Items	Total	Written	Passing	Progress
V1	6	6	6	100.00
V2	16	16	14	87.50
V2S	2	2	2	100.00
V3	1	1	1	100.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
97.72	99.07	96.67	100.00	100.00	98.83	98.33	91.14

Failure Buckets

• UVM_FATAL (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue has 3 failures:
  • Test adc_ctrl_filters_both has 3 failures.

    • 6.adc_ctrl_filters_both.114874310869515415838250761915701832989145570354655718100096661795339734939371
      Line 357, in log /container/opentitan-public/scratch/os_regression/adc_ctrl-sim-vcs/6.adc_ctrl_filters_both/latest/run.log

        UVM_FATAL @ 600000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 600000000000 ps hit, indicating a probable testbench issue
        UVM_INFO @ 600000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • 14.adc_ctrl_filters_both.78836774805741910849613306615065843868161351461729053160621893318882956752557
      Line 357, in log /container/opentitan-public/scratch/os_regression/adc_ctrl-sim-vcs/14.adc_ctrl_filters_both/latest/run.log

        UVM_FATAL @ 600000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 600000000000 ps hit, indicating a probable testbench issue
        UVM_INFO @ 600000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • ... and 1 more failures.

• Offending '(cfg_lp_sample_cnt_i > '0)' has 1 failures:
  • Test adc_ctrl_same_csr_outstanding has 1 failures.

    • 2.adc_ctrl_same_csr_outstanding.60017076728049984627132170309088417589494560646519199489306293834177279152654
      Line 332, in log /container/opentitan-public/scratch/os_regression/adc_ctrl-sim-vcs/2.adc_ctrl_same_csr_outstanding/latest/run.log

            Offending '(cfg_lp_sample_cnt_i > '0)'
        UVM_ERROR @ 2497753996 ps: (adc_ctrl_fsm.sv:382) [ASSERT FAILED] LpSampleCntCfg_M
        UVM_INFO @ 2497753996 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

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