ADC_CTRL Simulation Results

Tuesday August 06 2024 23:02:29 UTC

GitHub Revision: 5fd4ecc0fc

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 56304622830272859824235340993951659280265419461975949533183046575604373639200

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	adc_ctrl_smoke	15.220s	5.809ms	50	50	100.00
V1	csr_hw_reset	adc_ctrl_csr_hw_reset	2.410s	808.402us	5	5	100.00
V1	csr_rw	adc_ctrl_csr_rw	2.120s	570.595us	20	20	100.00
V1	csr_bit_bash	adc_ctrl_csr_bit_bash	3.266m	53.287ms	5	5	100.00
V1	csr_aliasing	adc_ctrl_csr_aliasing	3.410s	1.263ms	5	5	100.00
V1	csr_mem_rw_with_rand_reset	adc_ctrl_csr_mem_rw_with_rand_reset	2.110s	475.827us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	adc_ctrl_csr_rw	2.120s	570.595us	20	20	100.00
		adc_ctrl_csr_aliasing	3.410s	1.263ms	5	5	100.00
V1		TOTAL			105	105	100.00
V2	filters_polled	adc_ctrl_filters_polled	19.561m	493.298ms	50	50	100.00
V2	filters_polled_fixed	adc_ctrl_filters_polled_fixed	19.706m	508.016ms	50	50	100.00
V2	filters_interrupt	adc_ctrl_filters_interrupt	19.212m	483.218ms	50	50	100.00
V2	filters_interrupt_fixed	adc_ctrl_filters_interrupt_fixed	18.637m	499.668ms	50	50	100.00
V2	filters_wakeup	adc_ctrl_filters_wakeup	24.332m	608.701ms	50	50	100.00
V2	filters_wakeup_fixed	adc_ctrl_filters_wakeup_fixed	24.673m	591.005ms	50	50	100.00
V2	filters_both	adc_ctrl_filters_both	21.922m	600.000ms	49	50	98.00
V2	clock_gating	adc_ctrl_clock_gating	21.282m	551.673ms	50	50	100.00
V2	poweron_counter	adc_ctrl_poweron_counter	13.640s	5.735ms	50	50	100.00
V2	lowpower_counter	adc_ctrl_lowpower_counter	1.768m	43.704ms	50	50	100.00
V2	fsm_reset	adc_ctrl_fsm_reset	11.602m	130.246ms	50	50	100.00
V2	stress_all	adc_ctrl_stress_all	40.407m	969.274ms	50	50	100.00
V2	alert_test	adc_ctrl_alert_test	1.860s	503.981us	50	50	100.00
V2	intr_test	adc_ctrl_intr_test	1.930s	518.476us	50	50	100.00
V2	tl_d_oob_addr_access	adc_ctrl_tl_errors	3.380s	520.931us	20	20	100.00
V2	tl_d_illegal_access	adc_ctrl_tl_errors	3.380s	520.931us	20	20	100.00
V2	tl_d_outstanding_access	adc_ctrl_csr_hw_reset	2.410s	808.402us	5	5	100.00
		adc_ctrl_csr_rw	2.120s	570.595us	20	20	100.00
		adc_ctrl_csr_aliasing	3.410s	1.263ms	5	5	100.00
		adc_ctrl_same_csr_outstanding	17.910s	4.257ms	20	20	100.00
V2	tl_d_partial_access	adc_ctrl_csr_hw_reset	2.410s	808.402us	5	5	100.00
		adc_ctrl_csr_rw	2.120s	570.595us	20	20	100.00
		adc_ctrl_csr_aliasing	3.410s	1.263ms	5	5	100.00
		adc_ctrl_same_csr_outstanding	17.910s	4.257ms	20	20	100.00
V2		TOTAL			739	740	99.86
V2S	tl_intg_err	adc_ctrl_sec_cm	18.800s	8.159ms	5	5	100.00
		adc_ctrl_tl_intg_err	22.460s	8.505ms	20	20	100.00
V2S	sec_cm_bus_integrity	adc_ctrl_tl_intg_err	22.460s	8.505ms	20	20	100.00
V2S		TOTAL			25	25	100.00
V3	stress_all_with_rand_reset	adc_ctrl_stress_all_with_rand_reset	5.800m	1.333s	50	50	100.00
V3		TOTAL			50	50	100.00
		TOTAL			919	920	99.89

Testplan Progress

Items	Total	Written	Passing	Progress
V1	6	6	6	100.00
V2	16	16	15	93.75
V2S	2	2	2	100.00
V3	1	1	1	100.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
97.71	99.07	96.67	100.00	100.00	98.83	98.33	91.09

Failure Buckets

• UVM_FATAL (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue has 1 failures:
  • Test adc_ctrl_filters_both has 1 failures.

    • 45.adc_ctrl_filters_both.27888417701763681293383076089245163871014520734222722070725561433855829210727
      Line 357, in log /container/opentitan-public/scratch/os_regression/adc_ctrl-sim-vcs/45.adc_ctrl_filters_both/latest/run.log

        UVM_FATAL @ 600000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 600000000000 ps hit, indicating a probable testbench issue
        UVM_INFO @ 600000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

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