ADC_CTRL Simulation Results

Wednesday August 07 2024 23:02:33 UTC

GitHub Revision: `bbf435ceff`

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 6888687353677204195542416712589698377810102273194685652880785004967849651007

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	adc_ctrl_smoke	15.300s	6.052ms	50	50	100.00
V1	csr_hw_reset	adc_ctrl_csr_hw_reset	2.550s	753.996us	5	5	100.00
V1	csr_rw	adc_ctrl_csr_rw	1.840s	464.659us	20	20	100.00
V1	csr_bit_bash	adc_ctrl_csr_bit_bash	1.789m	52.684ms	5	5	100.00
V1	csr_aliasing	adc_ctrl_csr_aliasing	3.990s	1.439ms	5	5	100.00
V1	csr_mem_rw_with_rand_reset	adc_ctrl_csr_mem_rw_with_rand_reset	2.250s	590.627us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	adc_ctrl_csr_rw	1.840s	464.659us	20	20	100.00
		adc_ctrl_csr_aliasing	3.990s	1.439ms	5	5	100.00
V1		TOTAL			105	105	100.00
V2	filters_polled	adc_ctrl_filters_polled	18.571m	477.265ms	50	50	100.00
V2	filters_polled_fixed	adc_ctrl_filters_polled_fixed	19.053m	499.604ms	50	50	100.00
V2	filters_interrupt	adc_ctrl_filters_interrupt	19.874m	503.218ms	50	50	100.00
V2	filters_interrupt_fixed	adc_ctrl_filters_interrupt_fixed	20.067m	497.411ms	50	50	100.00
V2	filters_wakeup	adc_ctrl_filters_wakeup	23.489m	623.682ms	50	50	100.00
V2	filters_wakeup_fixed	adc_ctrl_filters_wakeup_fixed	23.953m	621.189ms	50	50	100.00
V2	filters_both	adc_ctrl_filters_both	21.120m	544.873ms	49	50	98.00
V2	clock_gating	adc_ctrl_clock_gating	20.416m	498.316ms	50	50	100.00
V2	poweron_counter	adc_ctrl_poweron_counter	13.380s	5.205ms	50	50	100.00
V2	lowpower_counter	adc_ctrl_lowpower_counter	1.700m	43.990ms	50	50	100.00
V2	fsm_reset	adc_ctrl_fsm_reset	12.059m	151.201ms	50	50	100.00
V2	stress_all	adc_ctrl_stress_all	37.125m	1.720s	50	50	100.00
V2	alert_test	adc_ctrl_alert_test	1.790s	505.608us	50	50	100.00
V2	intr_test	adc_ctrl_intr_test	1.860s	513.048us	50	50	100.00
V2	tl_d_oob_addr_access	adc_ctrl_tl_errors	3.350s	674.946us	20	20	100.00
V2	tl_d_illegal_access	adc_ctrl_tl_errors	3.350s	674.946us	20	20	100.00
V2	tl_d_outstanding_access	adc_ctrl_csr_hw_reset	2.550s	753.996us	5	5	100.00
		adc_ctrl_csr_rw	1.840s	464.659us	20	20	100.00
		adc_ctrl_csr_aliasing	3.990s	1.439ms	5	5	100.00
		adc_ctrl_same_csr_outstanding	13.210s	4.166ms	20	20	100.00
V2	tl_d_partial_access	adc_ctrl_csr_hw_reset	2.550s	753.996us	5	5	100.00
		adc_ctrl_csr_rw	1.840s	464.659us	20	20	100.00
		adc_ctrl_csr_aliasing	3.990s	1.439ms	5	5	100.00
		adc_ctrl_same_csr_outstanding	13.210s	4.166ms	20	20	100.00
V2		TOTAL			739	740	99.86
V2S	tl_intg_err	adc_ctrl_sec_cm	17.690s	7.809ms	5	5	100.00
		adc_ctrl_tl_intg_err	23.580s	8.897ms	20	20	100.00
V2S	sec_cm_bus_integrity	adc_ctrl_tl_intg_err	23.580s	8.897ms	20	20	100.00
V2S		TOTAL			25	25	100.00
V3	stress_all_with_rand_reset	adc_ctrl_stress_all_with_rand_reset	8.177m	197.026ms	49	50	98.00
V3		TOTAL			49	50	98.00
		TOTAL			918	920	99.78

Testplan Progress

Items	Total	Written	Passing	Progress
V1	6	6	6	100.00
V2	16	16	15	93.75
V2S	2	2	2	100.00
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
97.71	99.07	96.67	100.00	100.00	98.83	98.33	91.09

Failure Buckets

UVM_FATAL (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue has 1 failures:
- Test adc_ctrl_filters_both has 1 failures.
  - 47.adc_ctrl_filters_both.85824544729237693831874412033052825233919533932824880172130787041059609302394
    Line 357, in log /container/opentitan-public/scratch/os_regression/adc_ctrl-sim-vcs/47.adc_ctrl_filters_both/latest/run.log
```
  UVM_FATAL @ 600000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 600000000000 ps hit, indicating a probable testbench issue
  UVM_INFO @ 600000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
Offending '(np_sample_cnt_q == '0)' has 1 failures:
- Test adc_ctrl_stress_all_with_rand_reset has 1 failures.
  - 49.adc_ctrl_stress_all_with_rand_reset.72187114044880760154995888691264887130886755641965178559118380399835404544728
    Line 536, in log /container/opentitan-public/scratch/os_regression/adc_ctrl-sim-vcs/49.adc_ctrl_stress_all_with_rand_reset/latest/run.log
```
      Offending '(np_sample_cnt_q == '0)'
  UVM_ERROR @ 135581173387 ps: (adc_ctrl_fsm.sv:384) [ASSERT FAILED] NpCntClrPwrDn_A
  UVM_INFO @ 135581173387 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

ADC_CTRL Simulation Results

Wednesday August 07 2024 23:02:33 UTC

GitHub Revision: bbf435ceff

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 6888687353677204195542416712589698377810102273194685652880785004967849651007

Test Results

Testplan Progress

Coverage Results

Coverage Dashboard

Failure Buckets

Past Results

GitHub Revision: `bbf435ceff`