ADC_CTRL Simulation Results

Thursday August 08 2024 23:02:08 UTC

GitHub Revision: `3707c48f56`

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 96859198578252641766218135484681220968075710602306197013001824903089223290045

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	adc_ctrl_smoke	15.650s	5.698ms	50	50	100.00
V1	csr_hw_reset	adc_ctrl_csr_hw_reset	3.920s	1.305ms	5	5	100.00
V1	csr_rw	adc_ctrl_csr_rw	2.100s	524.386us	20	20	100.00
V1	csr_bit_bash	adc_ctrl_csr_bit_bash	35.470s	53.428ms	5	5	100.00
V1	csr_aliasing	adc_ctrl_csr_aliasing	3.230s	794.732us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	adc_ctrl_csr_mem_rw_with_rand_reset	2.000s	468.659us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	adc_ctrl_csr_rw	2.100s	524.386us	20	20	100.00
		adc_ctrl_csr_aliasing	3.230s	794.732us	5	5	100.00
V1		TOTAL			105	105	100.00
V2	filters_polled	adc_ctrl_filters_polled	19.742m	490.113ms	50	50	100.00
V2	filters_polled_fixed	adc_ctrl_filters_polled_fixed	20.460m	503.687ms	50	50	100.00
V2	filters_interrupt	adc_ctrl_filters_interrupt	19.424m	508.908ms	50	50	100.00
V2	filters_interrupt_fixed	adc_ctrl_filters_interrupt_fixed	19.334m	498.370ms	50	50	100.00
V2	filters_wakeup	adc_ctrl_filters_wakeup	23.498m	618.869ms	50	50	100.00
V2	filters_wakeup_fixed	adc_ctrl_filters_wakeup_fixed	23.834m	594.113ms	50	50	100.00
V2	filters_both	adc_ctrl_filters_both	21.534m	532.781ms	50	50	100.00
V2	clock_gating	adc_ctrl_clock_gating	20.001m	519.629ms	50	50	100.00
V2	poweron_counter	adc_ctrl_poweron_counter	12.550s	5.007ms	50	50	100.00
V2	lowpower_counter	adc_ctrl_lowpower_counter	1.732m	45.751ms	50	50	100.00
V2	fsm_reset	adc_ctrl_fsm_reset	12.272m	138.421ms	50	50	100.00
V2	stress_all	adc_ctrl_stress_all	37.099m	686.752ms	50	50	100.00
V2	alert_test	adc_ctrl_alert_test	1.720s	474.211us	50	50	100.00
V2	intr_test	adc_ctrl_intr_test	1.880s	527.689us	50	50	100.00
V2	tl_d_oob_addr_access	adc_ctrl_tl_errors	3.400s	516.178us	20	20	100.00
V2	tl_d_illegal_access	adc_ctrl_tl_errors	3.400s	516.178us	20	20	100.00
V2	tl_d_outstanding_access	adc_ctrl_csr_hw_reset	3.920s	1.305ms	5	5	100.00
		adc_ctrl_csr_rw	2.100s	524.386us	20	20	100.00
		adc_ctrl_csr_aliasing	3.230s	794.732us	5	5	100.00
		adc_ctrl_same_csr_outstanding	12.100s	4.903ms	20	20	100.00
V2	tl_d_partial_access	adc_ctrl_csr_hw_reset	3.920s	1.305ms	5	5	100.00
		adc_ctrl_csr_rw	2.100s	524.386us	20	20	100.00
		adc_ctrl_csr_aliasing	3.230s	794.732us	5	5	100.00
		adc_ctrl_same_csr_outstanding	12.100s	4.903ms	20	20	100.00
V2		TOTAL			740	740	100.00
V2S	tl_intg_err	adc_ctrl_sec_cm	18.280s	8.387ms	5	5	100.00
		adc_ctrl_tl_intg_err	21.530s	8.763ms	20	20	100.00
V2S	sec_cm_bus_integrity	adc_ctrl_tl_intg_err	21.530s	8.763ms	20	20	100.00
V2S		TOTAL			25	25	100.00
V3	stress_all_with_rand_reset	adc_ctrl_stress_all_with_rand_reset	15.662m	818.479ms	48	50	96.00
V3		TOTAL			48	50	96.00
		TOTAL			918	920	99.78

Testplan Progress

Items	Total	Written	Passing	Progress
V1	6	6	6	100.00
V2	16	16	16	100.00
V2S	2	2	2	100.00
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
97.66	99.07	96.67	100.00	100.00	98.83	98.33	90.72

Failure Buckets

UVM_ERROR (adc_ctrl_scoreboard.sv:405) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) reg name: adc_ctrl_reg_block.filter_status has 1 failures:
- Test adc_ctrl_stress_all_with_rand_reset has 1 failures.
  - 12.adc_ctrl_stress_all_with_rand_reset.112480485171778921996024385826162588636042836661074956927226753439709578019967
    Line 424, in log /container/opentitan-public/scratch/os_regression/adc_ctrl-sim-vcs/12.adc_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 24506861965 ps: (adc_ctrl_scoreboard.sv:405) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (0 [0x0] vs 94 [0x5e]) reg name: adc_ctrl_reg_block.filter_status
  UVM_INFO @ 24506861965 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (adc_ctrl_scoreboard.sv:137) [scoreboard] Check failed m_wakeup == m_expected_wakeup (* [*] vs * [*]) has 1 failures:
- Test adc_ctrl_stress_all_with_rand_reset has 1 failures.
  - 49.adc_ctrl_stress_all_with_rand_reset.3269838377778962859376815017306130263196139672280123895942666869872651174366
    Line 448, in log /container/opentitan-public/scratch/os_regression/adc_ctrl-sim-vcs/49.adc_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 91298190114 ps: (adc_ctrl_scoreboard.sv:137) [uvm_test_top.env.scoreboard] Check failed m_wakeup == m_expected_wakeup (1 [0x1] vs 0 [0x0])
  UVM_INFO @ 91298190114 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

ADC_CTRL Simulation Results

Thursday August 08 2024 23:02:08 UTC

GitHub Revision: 3707c48f56

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 96859198578252641766218135484681220968075710602306197013001824903089223290045

Test Results

Testplan Progress

Coverage Results

Coverage Dashboard

Failure Buckets

Past Results

GitHub Revision: `3707c48f56`