ADC_CTRL Simulation Results

Friday August 09 2024 23:02:07 UTC

GitHub Revision: 07b417ef03

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 39866585070056138360117926942905553094756411441088058786676399955088054585836

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	adc_ctrl_smoke	16.480s	6.155ms	50	50	100.00
V1	csr_hw_reset	adc_ctrl_csr_hw_reset	1.500s	1.425ms	5	5	100.00
V1	csr_rw	adc_ctrl_csr_rw	1.900s	523.099us	20	20	100.00
V1	csr_bit_bash	adc_ctrl_csr_bit_bash	1.491m	20.852ms	5	5	100.00
V1	csr_aliasing	adc_ctrl_csr_aliasing	4.210s	965.001us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	adc_ctrl_csr_mem_rw_with_rand_reset	2.160s	529.253us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	adc_ctrl_csr_rw	1.900s	523.099us	20	20	100.00
		adc_ctrl_csr_aliasing	4.210s	965.001us	5	5	100.00
V1		TOTAL			105	105	100.00
V2	filters_polled	adc_ctrl_filters_polled	19.662m	496.021ms	50	50	100.00
V2	filters_polled_fixed	adc_ctrl_filters_polled_fixed	20.282m	496.979ms	50	50	100.00
V2	filters_interrupt	adc_ctrl_filters_interrupt	20.152m	492.985ms	50	50	100.00
V2	filters_interrupt_fixed	adc_ctrl_filters_interrupt_fixed	20.081m	479.609ms	50	50	100.00
V2	filters_wakeup	adc_ctrl_filters_wakeup	27.151m	685.674ms	50	50	100.00
V2	filters_wakeup_fixed	adc_ctrl_filters_wakeup_fixed	24.168m	609.903ms	50	50	100.00
V2	filters_both	adc_ctrl_filters_both	23.354m	600.000ms	48	50	96.00
V2	clock_gating	adc_ctrl_clock_gating	17.115m	527.012ms	50	50	100.00
V2	poweron_counter	adc_ctrl_poweron_counter	14.280s	5.437ms	50	50	100.00
V2	lowpower_counter	adc_ctrl_lowpower_counter	1.846m	44.853ms	50	50	100.00
V2	fsm_reset	adc_ctrl_fsm_reset	9.889m	134.010ms	50	50	100.00
V2	stress_all	adc_ctrl_stress_all	41.053m	4.025s	50	50	100.00
V2	alert_test	adc_ctrl_alert_test	1.770s	524.145us	50	50	100.00
V2	intr_test	adc_ctrl_intr_test	1.870s	510.595us	50	50	100.00
V2	tl_d_oob_addr_access	adc_ctrl_tl_errors	4.030s	541.605us	20	20	100.00
V2	tl_d_illegal_access	adc_ctrl_tl_errors	4.030s	541.605us	20	20	100.00
V2	tl_d_outstanding_access	adc_ctrl_csr_hw_reset	1.500s	1.425ms	5	5	100.00
		adc_ctrl_csr_rw	1.900s	523.099us	20	20	100.00
		adc_ctrl_csr_aliasing	4.210s	965.001us	5	5	100.00
		adc_ctrl_same_csr_outstanding	15.430s	4.175ms	20	20	100.00
V2	tl_d_partial_access	adc_ctrl_csr_hw_reset	1.500s	1.425ms	5	5	100.00
		adc_ctrl_csr_rw	1.900s	523.099us	20	20	100.00
		adc_ctrl_csr_aliasing	4.210s	965.001us	5	5	100.00
		adc_ctrl_same_csr_outstanding	15.430s	4.175ms	20	20	100.00
V2		TOTAL			738	740	99.73
V2S	tl_intg_err	adc_ctrl_sec_cm	19.230s	7.799ms	5	5	100.00
		adc_ctrl_tl_intg_err	21.240s	8.444ms	20	20	100.00
V2S	sec_cm_bus_integrity	adc_ctrl_tl_intg_err	21.240s	8.444ms	20	20	100.00
V2S		TOTAL			25	25	100.00
V3	stress_all_with_rand_reset	adc_ctrl_stress_all_with_rand_reset	10.928m	936.590ms	49	50	98.00
V3		TOTAL			49	50	98.00
		TOTAL			917	920	99.67

Testplan Progress

Items	Total	Written	Passing	Progress
V1	6	6	6	100.00
V2	16	16	15	93.75
V2S	2	2	2	100.00
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
97.79	99.07	96.67	100.00	100.00	98.83	98.33	91.61

Failure Buckets

• UVM_FATAL (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue has 2 failures:

  • Test adc_ctrl_filters_both has 2 failures.

    • 1.adc_ctrl_filters_both.45152116430159163524042825729081840418410443109487847260736784303841868829979
      Line 357, in log /container/opentitan-public/scratch/os_regression/adc_ctrl-sim-vcs/1.adc_ctrl_filters_both/latest/run.log

        UVM_FATAL @ 600000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 600000000000 ps hit, indicating a probable testbench issue
        UVM_INFO @ 600000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • 49.adc_ctrl_filters_both.85430031254563028276928626779485261904708069167840211255352359863103187473431
      Line 357, in log /container/opentitan-public/scratch/os_regression/adc_ctrl-sim-vcs/49.adc_ctrl_filters_both/latest/run.log

        UVM_FATAL @ 600000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 600000000000 ps hit, indicating a probable testbench issue
        UVM_INFO @ 600000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_ERROR (adc_ctrl_scoreboard.sv:405) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) reg name: adc_ctrl_reg_block.filter_status has 1 failures:

  • Test adc_ctrl_stress_all_with_rand_reset has 1 failures.

    • 23.adc_ctrl_stress_all_with_rand_reset.95595076713732695967771821827601217737515941546768303128018586100461533496489
      Line 490, in log /container/opentitan-public/scratch/os_regression/adc_ctrl-sim-vcs/23.adc_ctrl_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 145942815033 ps: (adc_ctrl_scoreboard.sv:405) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (0 [0x0] vs 65 [0x41]) reg name: adc_ctrl_reg_block.filter_status
        UVM_INFO @ 145942815033 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

Past Results

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