ADC_CTRL Simulation Results

Saturday August 10 2024 23:02:23 UTC

GitHub Revision: 07b417ef03

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 2196818177928134427831197337249851347498377272679561983541244979366753055772

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	adc_ctrl_smoke	15.860s	6.037ms	50	50	100.00
V1	csr_hw_reset	adc_ctrl_csr_hw_reset	3.420s	1.138ms	5	5	100.00
V1	csr_rw	adc_ctrl_csr_rw	1.870s	455.901us	20	20	100.00
V1	csr_bit_bash	adc_ctrl_csr_bit_bash	1.657m	26.658ms	5	5	100.00
V1	csr_aliasing	adc_ctrl_csr_aliasing	4.690s	1.041ms	5	5	100.00
V1	csr_mem_rw_with_rand_reset	adc_ctrl_csr_mem_rw_with_rand_reset	2.130s	554.802us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	adc_ctrl_csr_rw	1.870s	455.901us	20	20	100.00
		adc_ctrl_csr_aliasing	4.690s	1.041ms	5	5	100.00
V1		TOTAL			105	105	100.00
V2	filters_polled	adc_ctrl_filters_polled	19.263m	491.595ms	50	50	100.00
V2	filters_polled_fixed	adc_ctrl_filters_polled_fixed	19.521m	499.317ms	50	50	100.00
V2	filters_interrupt	adc_ctrl_filters_interrupt	21.136m	506.841ms	50	50	100.00
V2	filters_interrupt_fixed	adc_ctrl_filters_interrupt_fixed	19.964m	493.035ms	50	50	100.00
V2	filters_wakeup	adc_ctrl_filters_wakeup	21.642m	557.079ms	50	50	100.00
V2	filters_wakeup_fixed	adc_ctrl_filters_wakeup_fixed	23.131m	616.047ms	50	50	100.00
V2	filters_both	adc_ctrl_filters_both	21.545m	600.000ms	49	50	98.00
V2	clock_gating	adc_ctrl_clock_gating	18.856m	494.709ms	50	50	100.00
V2	poweron_counter	adc_ctrl_poweron_counter	13.550s	4.950ms	50	50	100.00
V2	lowpower_counter	adc_ctrl_lowpower_counter	1.821m	45.427ms	50	50	100.00
V2	fsm_reset	adc_ctrl_fsm_reset	11.771m	141.355ms	50	50	100.00
V2	stress_all	adc_ctrl_stress_all	51.364m	4.559s	50	50	100.00
V2	alert_test	adc_ctrl_alert_test	1.800s	473.443us	50	50	100.00
V2	intr_test	adc_ctrl_intr_test	1.930s	499.637us	50	50	100.00
V2	tl_d_oob_addr_access	adc_ctrl_tl_errors	4.240s	525.308us	20	20	100.00
V2	tl_d_illegal_access	adc_ctrl_tl_errors	4.240s	525.308us	20	20	100.00
V2	tl_d_outstanding_access	adc_ctrl_csr_hw_reset	3.420s	1.138ms	5	5	100.00
		adc_ctrl_csr_rw	1.870s	455.901us	20	20	100.00
		adc_ctrl_csr_aliasing	4.690s	1.041ms	5	5	100.00
		adc_ctrl_same_csr_outstanding	10.410s	4.720ms	20	20	100.00
V2	tl_d_partial_access	adc_ctrl_csr_hw_reset	3.420s	1.138ms	5	5	100.00
		adc_ctrl_csr_rw	1.870s	455.901us	20	20	100.00
		adc_ctrl_csr_aliasing	4.690s	1.041ms	5	5	100.00
		adc_ctrl_same_csr_outstanding	10.410s	4.720ms	20	20	100.00
V2		TOTAL			739	740	99.86
V2S	tl_intg_err	adc_ctrl_sec_cm	18.000s	7.861ms	5	5	100.00
		adc_ctrl_tl_intg_err	20.200s	7.951ms	20	20	100.00
V2S	sec_cm_bus_integrity	adc_ctrl_tl_intg_err	20.200s	7.951ms	20	20	100.00
V2S		TOTAL			25	25	100.00
V3	stress_all_with_rand_reset	adc_ctrl_stress_all_with_rand_reset	10.910m	665.890ms	50	50	100.00
V3		TOTAL			50	50	100.00
		TOTAL			919	920	99.89

Testplan Progress

Items	Total	Written	Passing	Progress
V1	6	6	6	100.00
V2	16	16	15	93.75
V2S	2	2	2	100.00
V3	1	1	1	100.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
97.69	99.07	96.67	100.00	100.00	98.83	98.33	90.92

Failure Buckets

• UVM_FATAL (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue has 1 failures:
  • Test adc_ctrl_filters_both has 1 failures.

    • 32.adc_ctrl_filters_both.55972763757471187926453497080945787561814343606433571754399571083493993550183
      Line 357, in log /container/opentitan-public/scratch/os_regression/adc_ctrl-sim-vcs/32.adc_ctrl_filters_both/latest/run.log

        UVM_FATAL @ 600000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 600000000000 ps hit, indicating a probable testbench issue
        UVM_INFO @ 600000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

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