ADC_CTRL Simulation Results

Sunday August 11 2024 23:02:21 UTC

GitHub Revision: `07b417ef03`

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 6142445146730822936893044599112392910298048088673599708943858624824800218011

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	adc_ctrl_smoke	15.250s	5.855ms	50	50	100.00
V1	csr_hw_reset	adc_ctrl_csr_hw_reset	3.230s	1.083ms	5	5	100.00
V1	csr_rw	adc_ctrl_csr_rw	1.980s	513.562us	20	20	100.00
V1	csr_bit_bash	adc_ctrl_csr_bit_bash	2.330m	40.499ms	5	5	100.00
V1	csr_aliasing	adc_ctrl_csr_aliasing	2.760s	893.265us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	adc_ctrl_csr_mem_rw_with_rand_reset	2.250s	557.366us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	adc_ctrl_csr_rw	1.980s	513.562us	20	20	100.00
		adc_ctrl_csr_aliasing	2.760s	893.265us	5	5	100.00
V1		TOTAL			105	105	100.00
V2	filters_polled	adc_ctrl_filters_polled	19.723m	511.357ms	50	50	100.00
V2	filters_polled_fixed	adc_ctrl_filters_polled_fixed	20.311m	496.145ms	50	50	100.00
V2	filters_interrupt	adc_ctrl_filters_interrupt	20.274m	496.221ms	50	50	100.00
V2	filters_interrupt_fixed	adc_ctrl_filters_interrupt_fixed	19.301m	485.440ms	50	50	100.00
V2	filters_wakeup	adc_ctrl_filters_wakeup	22.420m	554.153ms	50	50	100.00
V2	filters_wakeup_fixed	adc_ctrl_filters_wakeup_fixed	23.307m	602.927ms	50	50	100.00
V2	filters_both	adc_ctrl_filters_both	21.799m	600.000ms	49	50	98.00
V2	clock_gating	adc_ctrl_clock_gating	19.732m	526.301ms	50	50	100.00
V2	poweron_counter	adc_ctrl_poweron_counter	12.740s	5.046ms	50	50	100.00
V2	lowpower_counter	adc_ctrl_lowpower_counter	1.718m	43.934ms	50	50	100.00
V2	fsm_reset	adc_ctrl_fsm_reset	12.316m	144.490ms	50	50	100.00
V2	stress_all	adc_ctrl_stress_all	35.541m	623.563ms	50	50	100.00
V2	alert_test	adc_ctrl_alert_test	1.860s	505.822us	50	50	100.00
V2	intr_test	adc_ctrl_intr_test	1.820s	510.667us	50	50	100.00
V2	tl_d_oob_addr_access	adc_ctrl_tl_errors	3.700s	605.414us	20	20	100.00
V2	tl_d_illegal_access	adc_ctrl_tl_errors	3.700s	605.414us	20	20	100.00
V2	tl_d_outstanding_access	adc_ctrl_csr_hw_reset	3.230s	1.083ms	5	5	100.00
		adc_ctrl_csr_rw	1.980s	513.562us	20	20	100.00
		adc_ctrl_csr_aliasing	2.760s	893.265us	5	5	100.00
		adc_ctrl_same_csr_outstanding	17.560s	4.622ms	20	20	100.00
V2	tl_d_partial_access	adc_ctrl_csr_hw_reset	3.230s	1.083ms	5	5	100.00
		adc_ctrl_csr_rw	1.980s	513.562us	20	20	100.00
		adc_ctrl_csr_aliasing	2.760s	893.265us	5	5	100.00
		adc_ctrl_same_csr_outstanding	17.560s	4.622ms	20	20	100.00
V2		TOTAL			739	740	99.86
V2S	tl_intg_err	adc_ctrl_sec_cm	9.620s	8.006ms	5	5	100.00
		adc_ctrl_tl_intg_err	21.790s	8.797ms	20	20	100.00
V2S	sec_cm_bus_integrity	adc_ctrl_tl_intg_err	21.790s	8.797ms	20	20	100.00
V2S		TOTAL			25	25	100.00
V3	stress_all_with_rand_reset	adc_ctrl_stress_all_with_rand_reset	13.603m	981.428ms	50	50	100.00
V3		TOTAL			50	50	100.00
		TOTAL			919	920	99.89

Testplan Progress

Items	Total	Written	Passing	Progress
V1	6	6	6	100.00
V2	16	16	15	93.75
V2S	2	2	2	100.00
V3	1	1	1	100.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
97.74	99.07	96.67	100.00	100.00	98.83	98.33	91.32

Failure Buckets

UVM_FATAL (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue has 1 failures:
- Test adc_ctrl_filters_both has 1 failures.
  - 8.adc_ctrl_filters_both.107433062853000129887457702223941181342980442328086123951507058451252385809551
    Line 357, in log /container/opentitan-public/scratch/os_regression/adc_ctrl-sim-vcs/8.adc_ctrl_filters_both/latest/run.log
```
  UVM_FATAL @ 600000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 600000000000 ps hit, indicating a probable testbench issue
  UVM_INFO @ 600000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

ADC_CTRL Simulation Results

Sunday August 11 2024 23:02:21 UTC

GitHub Revision: 07b417ef03

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 6142445146730822936893044599112392910298048088673599708943858624824800218011

Test Results

Testplan Progress

Coverage Results

Coverage Dashboard

Failure Buckets

Past Results

GitHub Revision: `07b417ef03`