ADC_CTRL Simulation Results

Monday August 12 2024 23:02:30 UTC

GitHub Revision: `c082b8981f`

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 107262934208806092150901079363789224644653433402469901409990667510497383888850

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	adc_ctrl_smoke	16.240s	5.882ms	50	50	100.00
V1	csr_hw_reset	adc_ctrl_csr_hw_reset	1.460s	1.328ms	5	5	100.00
V1	csr_rw	adc_ctrl_csr_rw	2.060s	575.757us	20	20	100.00
V1	csr_bit_bash	adc_ctrl_csr_bit_bash	57.380s	26.878ms	5	5	100.00
V1	csr_aliasing	adc_ctrl_csr_aliasing	6.110s	1.366ms	5	5	100.00
V1	csr_mem_rw_with_rand_reset	adc_ctrl_csr_mem_rw_with_rand_reset	2.390s	589.444us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	adc_ctrl_csr_rw	2.060s	575.757us	20	20	100.00
		adc_ctrl_csr_aliasing	6.110s	1.366ms	5	5	100.00
V1		TOTAL			105	105	100.00
V2	filters_polled	adc_ctrl_filters_polled	19.283m	500.249ms	50	50	100.00
V2	filters_polled_fixed	adc_ctrl_filters_polled_fixed	19.957m	497.804ms	50	50	100.00
V2	filters_interrupt	adc_ctrl_filters_interrupt	20.464m	499.472ms	50	50	100.00
V2	filters_interrupt_fixed	adc_ctrl_filters_interrupt_fixed	20.701m	500.703ms	50	50	100.00
V2	filters_wakeup	adc_ctrl_filters_wakeup	27.127m	685.270ms	50	50	100.00
V2	filters_wakeup_fixed	adc_ctrl_filters_wakeup_fixed	24.185m	590.888ms	50	50	100.00
V2	filters_both	adc_ctrl_filters_both	23.395m	562.747ms	48	50	96.00
V2	clock_gating	adc_ctrl_clock_gating	19.065m	535.279ms	50	50	100.00
V2	poweron_counter	adc_ctrl_poweron_counter	13.380s	5.316ms	50	50	100.00
V2	lowpower_counter	adc_ctrl_lowpower_counter	1.777m	45.458ms	50	50	100.00
V2	fsm_reset	adc_ctrl_fsm_reset	11.471m	130.757ms	50	50	100.00
V2	stress_all	adc_ctrl_stress_all	32.777m	630.794ms	50	50	100.00
V2	alert_test	adc_ctrl_alert_test	1.870s	479.035us	50	50	100.00
V2	intr_test	adc_ctrl_intr_test	2.010s	528.468us	50	50	100.00
V2	tl_d_oob_addr_access	adc_ctrl_tl_errors	3.190s	595.220us	20	20	100.00
V2	tl_d_illegal_access	adc_ctrl_tl_errors	3.190s	595.220us	20	20	100.00
V2	tl_d_outstanding_access	adc_ctrl_csr_hw_reset	1.460s	1.328ms	5	5	100.00
		adc_ctrl_csr_rw	2.060s	575.757us	20	20	100.00
		adc_ctrl_csr_aliasing	6.110s	1.366ms	5	5	100.00
		adc_ctrl_same_csr_outstanding	23.210s	4.524ms	20	20	100.00
V2	tl_d_partial_access	adc_ctrl_csr_hw_reset	1.460s	1.328ms	5	5	100.00
		adc_ctrl_csr_rw	2.060s	575.757us	20	20	100.00
		adc_ctrl_csr_aliasing	6.110s	1.366ms	5	5	100.00
		adc_ctrl_same_csr_outstanding	23.210s	4.524ms	20	20	100.00
V2		TOTAL			738	740	99.73
V2S	tl_intg_err	adc_ctrl_sec_cm	18.930s	7.653ms	5	5	100.00
		adc_ctrl_tl_intg_err	19.620s	8.674ms	20	20	100.00
V2S	sec_cm_bus_integrity	adc_ctrl_tl_intg_err	19.620s	8.674ms	20	20	100.00
V2S		TOTAL			25	25	100.00
V3	stress_all_with_rand_reset	adc_ctrl_stress_all_with_rand_reset	1.081m	731.851ms	50	50	100.00
V3		TOTAL			50	50	100.00
		TOTAL			918	920	99.78

Testplan Progress

Items	Total	Written	Passing	Progress
V1	6	6	6	100.00
V2	16	16	15	93.75
V2S	2	2	2	100.00
V3	1	1	1	100.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
97.70	99.07	96.67	100.00	100.00	98.83	98.33	91.02

Failure Buckets

UVM_FATAL (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue has 2 failures:
- Test adc_ctrl_filters_both has 2 failures.
  - 38.adc_ctrl_filters_both.68556203071903828976100113335544647990782617592449427202820635545637487442214
    Line 357, in log /container/opentitan-public/scratch/os_regression/adc_ctrl-sim-vcs/38.adc_ctrl_filters_both/latest/run.log
```
  UVM_FATAL @ 600000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 600000000000 ps hit, indicating a probable testbench issue
  UVM_INFO @ 600000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 49.adc_ctrl_filters_both.61492121032382400879156286092498928387135773154354168995736500715032866921443
    Line 357, in log /container/opentitan-public/scratch/os_regression/adc_ctrl-sim-vcs/49.adc_ctrl_filters_both/latest/run.log
```
  UVM_FATAL @ 600000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 600000000000 ps hit, indicating a probable testbench issue
  UVM_INFO @ 600000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

ADC_CTRL Simulation Results

Monday August 12 2024 23:02:30 UTC

GitHub Revision: c082b8981f

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 107262934208806092150901079363789224644653433402469901409990667510497383888850

Test Results

Testplan Progress

Coverage Results

Coverage Dashboard

Failure Buckets

Past Results

GitHub Revision: `c082b8981f`