ADC_CTRL Simulation Results

Tuesday August 13 2024 23:04:47 UTC

GitHub Revision: `098010d125`

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 12185085088694708177096441863424670920996379189869351644310607217057882846251

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	adc_ctrl_smoke	16.470s	6.033ms	50	50	100.00
V1	csr_hw_reset	adc_ctrl_csr_hw_reset	3.050s	1.022ms	5	5	100.00
V1	csr_rw	adc_ctrl_csr_rw	2.020s	520.929us	20	20	100.00
V1	csr_bit_bash	adc_ctrl_csr_bit_bash	1.446m	26.347ms	5	5	100.00
V1	csr_aliasing	adc_ctrl_csr_aliasing	5.260s	1.360ms	5	5	100.00
V1	csr_mem_rw_with_rand_reset	adc_ctrl_csr_mem_rw_with_rand_reset	2.280s	602.588us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	adc_ctrl_csr_rw	2.020s	520.929us	20	20	100.00
		adc_ctrl_csr_aliasing	5.260s	1.360ms	5	5	100.00
V1		TOTAL			105	105	100.00
V2	filters_polled	adc_ctrl_filters_polled	18.777m	491.678ms	50	50	100.00
V2	filters_polled_fixed	adc_ctrl_filters_polled_fixed	19.302m	488.933ms	50	50	100.00
V2	filters_interrupt	adc_ctrl_filters_interrupt	20.034m	494.608ms	50	50	100.00
V2	filters_interrupt_fixed	adc_ctrl_filters_interrupt_fixed	17.934m	497.909ms	50	50	100.00
V2	filters_wakeup	adc_ctrl_filters_wakeup	21.285m	523.930ms	50	50	100.00
V2	filters_wakeup_fixed	adc_ctrl_filters_wakeup_fixed	23.570m	600.484ms	50	50	100.00
V2	filters_both	adc_ctrl_filters_both	20.467m	550.299ms	49	50	98.00
V2	clock_gating	adc_ctrl_clock_gating	21.396m	558.324ms	50	50	100.00
V2	poweron_counter	adc_ctrl_poweron_counter	13.240s	4.799ms	50	50	100.00
V2	lowpower_counter	adc_ctrl_lowpower_counter	1.702m	42.926ms	50	50	100.00
V2	fsm_reset	adc_ctrl_fsm_reset	11.554m	134.612ms	50	50	100.00
V2	stress_all	adc_ctrl_stress_all	37.907m	1.387s	50	50	100.00
V2	alert_test	adc_ctrl_alert_test	1.720s	496.492us	50	50	100.00
V2	intr_test	adc_ctrl_intr_test	1.870s	529.371us	50	50	100.00
V2	tl_d_oob_addr_access	adc_ctrl_tl_errors	3.780s	484.832us	20	20	100.00
V2	tl_d_illegal_access	adc_ctrl_tl_errors	3.780s	484.832us	20	20	100.00
V2	tl_d_outstanding_access	adc_ctrl_csr_hw_reset	3.050s	1.022ms	5	5	100.00
		adc_ctrl_csr_rw	2.020s	520.929us	20	20	100.00
		adc_ctrl_csr_aliasing	5.260s	1.360ms	5	5	100.00
		adc_ctrl_same_csr_outstanding	21.020s	5.236ms	20	20	100.00
V2	tl_d_partial_access	adc_ctrl_csr_hw_reset	3.050s	1.022ms	5	5	100.00
		adc_ctrl_csr_rw	2.020s	520.929us	20	20	100.00
		adc_ctrl_csr_aliasing	5.260s	1.360ms	5	5	100.00
		adc_ctrl_same_csr_outstanding	21.020s	5.236ms	20	20	100.00
V2		TOTAL			739	740	99.86
V2S	tl_intg_err	adc_ctrl_sec_cm	17.260s	7.235ms	5	5	100.00
		adc_ctrl_tl_intg_err	21.420s	8.352ms	20	20	100.00
V2S	sec_cm_bus_integrity	adc_ctrl_tl_intg_err	21.420s	8.352ms	20	20	100.00
V2S		TOTAL			25	25	100.00
V3	stress_all_with_rand_reset	adc_ctrl_stress_all_with_rand_reset	35.140s	9.526ms	50	50	100.00
V3		TOTAL			50	50	100.00
		TOTAL			919	920	99.89

Testplan Progress

Items	Total	Written	Passing	Progress
V1	6	6	6	100.00
V2	16	16	15	93.75
V2S	2	2	2	100.00
V3	1	1	1	100.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
97.78	99.07	96.67	100.00	100.00	98.83	98.33	91.54

Failure Buckets

UVM_FATAL (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue has 1 failures:
- Test adc_ctrl_filters_both has 1 failures.
  - 48.adc_ctrl_filters_both.20847936471992882911152471741383659762879502864667379509512444425262714502418
    Line 357, in log /container/opentitan-public/scratch/os_regression/adc_ctrl-sim-vcs/48.adc_ctrl_filters_both/latest/run.log
```
  UVM_FATAL @ 600000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 600000000000 ps hit, indicating a probable testbench issue
  UVM_INFO @ 600000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

ADC_CTRL Simulation Results

Tuesday August 13 2024 23:04:47 UTC

GitHub Revision: 098010d125

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 12185085088694708177096441863424670920996379189869351644310607217057882846251

Test Results

Testplan Progress

Coverage Results

Coverage Dashboard

Failure Buckets

Past Results

GitHub Revision: `098010d125`