ADC_CTRL Simulation Results

Wednesday August 14 2024 23:02:33 UTC

GitHub Revision: 584c3d46af

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 75916000169703078066460267353397937307391759551032957123310220571514951708138

Test Results

Stage Name Tests Max Job Runtime Simulated Time Passing Total Pass Rate
V1 smoke adc_ctrl_smoke 16.060s 6.166ms 50 50 100.00
V1 csr_hw_reset adc_ctrl_csr_hw_reset 3.610s 1.303ms 5 5 100.00
V1 csr_rw adc_ctrl_csr_rw 1.970s 505.308us 20 20 100.00
V1 csr_bit_bash adc_ctrl_csr_bit_bash 1.544m 42.054ms 5 5 100.00
V1 csr_aliasing adc_ctrl_csr_aliasing 4.080s 936.256us 5 5 100.00
V1 csr_mem_rw_with_rand_reset adc_ctrl_csr_mem_rw_with_rand_reset 2.100s 531.064us 20 20 100.00
V1 regwen_csr_and_corresponding_lockable_csr adc_ctrl_csr_rw 1.970s 505.308us 20 20 100.00
adc_ctrl_csr_aliasing 4.080s 936.256us 5 5 100.00
V1 TOTAL 105 105 100.00
V2 filters_polled adc_ctrl_filters_polled 19.683m 498.116ms 50 50 100.00
V2 filters_polled_fixed adc_ctrl_filters_polled_fixed 19.434m 493.389ms 50 50 100.00
V2 filters_interrupt adc_ctrl_filters_interrupt 20.208m 488.639ms 50 50 100.00
V2 filters_interrupt_fixed adc_ctrl_filters_interrupt_fixed 19.719m 499.651ms 50 50 100.00
V2 filters_wakeup adc_ctrl_filters_wakeup 24.305m 615.979ms 50 50 100.00
V2 filters_wakeup_fixed adc_ctrl_filters_wakeup_fixed 23.384m 581.234ms 50 50 100.00
V2 filters_both adc_ctrl_filters_both 22.339m 563.990ms 50 50 100.00
V2 clock_gating adc_ctrl_clock_gating 20.958m 540.117ms 50 50 100.00
V2 poweron_counter adc_ctrl_poweron_counter 13.390s 5.079ms 50 50 100.00
V2 lowpower_counter adc_ctrl_lowpower_counter 1.835m 46.985ms 50 50 100.00
V2 fsm_reset adc_ctrl_fsm_reset 12.328m 136.081ms 50 50 100.00
V2 stress_all adc_ctrl_stress_all 28.036m 597.539ms 50 50 100.00
V2 alert_test adc_ctrl_alert_test 1.720s 473.074us 50 50 100.00
V2 intr_test adc_ctrl_intr_test 1.890s 521.924us 50 50 100.00
V2 tl_d_oob_addr_access adc_ctrl_tl_errors 3.300s 394.865us 20 20 100.00
V2 tl_d_illegal_access adc_ctrl_tl_errors 3.300s 394.865us 20 20 100.00
V2 tl_d_outstanding_access adc_ctrl_csr_hw_reset 3.610s 1.303ms 5 5 100.00
adc_ctrl_csr_rw 1.970s 505.308us 20 20 100.00
adc_ctrl_csr_aliasing 4.080s 936.256us 5 5 100.00
adc_ctrl_same_csr_outstanding 11.140s 4.829ms 20 20 100.00
V2 tl_d_partial_access adc_ctrl_csr_hw_reset 3.610s 1.303ms 5 5 100.00
adc_ctrl_csr_rw 1.970s 505.308us 20 20 100.00
adc_ctrl_csr_aliasing 4.080s 936.256us 5 5 100.00
adc_ctrl_same_csr_outstanding 11.140s 4.829ms 20 20 100.00
V2 TOTAL 740 740 100.00
V2S tl_intg_err adc_ctrl_sec_cm 9.510s 3.974ms 5 5 100.00
adc_ctrl_tl_intg_err 23.030s 9.044ms 20 20 100.00
V2S sec_cm_bus_integrity adc_ctrl_tl_intg_err 23.030s 9.044ms 20 20 100.00
V2S TOTAL 25 25 100.00
V3 stress_all_with_rand_reset adc_ctrl_stress_all_with_rand_reset 1.036m 46.093ms 50 50 100.00
V3 TOTAL 50 50 100.00
TOTAL 920 920 100.00

Testplan Progress

Items Total Written Passing Progress
V1 6 6 6 100.00
V2 16 16 16 100.00
V2S 2 2 2 100.00
V3 1 1 1 100.00

Coverage Results

Coverage Dashboard

SCORE LINE COND TOGGLE FSM BRANCH ASSERT GROUP
97.78 99.07 96.67 100.00 100.00 98.83 98.33 91.56

Past Results