ADC_CTRL Simulation Results

Thursday August 15 2024 23:02:21 UTC

GitHub Revision: d09e282b26

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 47908880312501934977153450267828796412449789719488445881682136509150457490963

Test Results

Stage Name Tests Max Job Runtime Simulated Time Passing Total Pass Rate
V1 smoke adc_ctrl_smoke 16.060s 5.895ms 50 50 100.00
V1 csr_hw_reset adc_ctrl_csr_hw_reset 2.190s 709.416us 5 5 100.00
V1 csr_rw adc_ctrl_csr_rw 2.020s 542.858us 20 20 100.00
V1 csr_bit_bash adc_ctrl_csr_bit_bash 41.320s 53.148ms 5 5 100.00
V1 csr_aliasing adc_ctrl_csr_aliasing 3.370s 681.011us 5 5 100.00
V1 csr_mem_rw_with_rand_reset adc_ctrl_csr_mem_rw_with_rand_reset 2.110s 594.013us 20 20 100.00
V1 regwen_csr_and_corresponding_lockable_csr adc_ctrl_csr_rw 2.020s 542.858us 20 20 100.00
adc_ctrl_csr_aliasing 3.370s 681.011us 5 5 100.00
V1 TOTAL 105 105 100.00
V2 filters_polled adc_ctrl_filters_polled 19.885m 485.017ms 50 50 100.00
V2 filters_polled_fixed adc_ctrl_filters_polled_fixed 19.457m 495.351ms 50 50 100.00
V2 filters_interrupt adc_ctrl_filters_interrupt 19.616m 494.651ms 50 50 100.00
V2 filters_interrupt_fixed adc_ctrl_filters_interrupt_fixed 20.144m 496.352ms 50 50 100.00
V2 filters_wakeup adc_ctrl_filters_wakeup 24.505m 626.040ms 50 50 100.00
V2 filters_wakeup_fixed adc_ctrl_filters_wakeup_fixed 22.931m 610.102ms 50 50 100.00
V2 filters_both adc_ctrl_filters_both 21.283m 548.947ms 50 50 100.00
V2 clock_gating adc_ctrl_clock_gating 20.749m 513.401ms 50 50 100.00
V2 poweron_counter adc_ctrl_poweron_counter 13.460s 5.382ms 50 50 100.00
V2 lowpower_counter adc_ctrl_lowpower_counter 1.901m 48.755ms 50 50 100.00
V2 fsm_reset adc_ctrl_fsm_reset 11.397m 131.590ms 50 50 100.00
V2 stress_all adc_ctrl_stress_all 24.808m 465.816ms 50 50 100.00
V2 alert_test adc_ctrl_alert_test 1.910s 498.943us 50 50 100.00
V2 intr_test adc_ctrl_intr_test 1.880s 512.523us 50 50 100.00
V2 tl_d_oob_addr_access adc_ctrl_tl_errors 3.480s 536.907us 20 20 100.00
V2 tl_d_illegal_access adc_ctrl_tl_errors 3.480s 536.907us 20 20 100.00
V2 tl_d_outstanding_access adc_ctrl_csr_hw_reset 2.190s 709.416us 5 5 100.00
adc_ctrl_csr_rw 2.020s 542.858us 20 20 100.00
adc_ctrl_csr_aliasing 3.370s 681.011us 5 5 100.00
adc_ctrl_same_csr_outstanding 19.660s 5.128ms 20 20 100.00
V2 tl_d_partial_access adc_ctrl_csr_hw_reset 2.190s 709.416us 5 5 100.00
adc_ctrl_csr_rw 2.020s 542.858us 20 20 100.00
adc_ctrl_csr_aliasing 3.370s 681.011us 5 5 100.00
adc_ctrl_same_csr_outstanding 19.660s 5.128ms 20 20 100.00
V2 TOTAL 740 740 100.00
V2S tl_intg_err adc_ctrl_sec_cm 19.610s 7.788ms 5 5 100.00
adc_ctrl_tl_intg_err 21.380s 8.085ms 20 20 100.00
V2S sec_cm_bus_integrity adc_ctrl_tl_intg_err 21.380s 8.085ms 20 20 100.00
V2S TOTAL 25 25 100.00
V3 stress_all_with_rand_reset adc_ctrl_stress_all_with_rand_reset 1.059m 1.318s 50 50 100.00
V3 TOTAL 50 50 100.00
TOTAL 920 920 100.00

Testplan Progress

Items Total Written Passing Progress
V1 6 6 6 100.00
V2 16 16 16 100.00
V2S 2 2 2 100.00
V3 1 1 1 100.00

Coverage Results

Coverage Dashboard

SCORE LINE COND TOGGLE FSM BRANCH ASSERT GROUP
97.67 99.07 96.67 100.00 100.00 98.83 98.33 90.77

Past Results