ADC_CTRL Simulation Results

Friday August 16 2024 23:02:10 UTC

GitHub Revision: 76588857da

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 107397868712693014844033025164446565408841343499325418676943424680076749785789

Test Results

Stage Name Tests Max Job Runtime Simulated Time Passing Total Pass Rate
V1 smoke adc_ctrl_smoke 14.930s 6.143ms 50 50 100.00
V1 csr_hw_reset adc_ctrl_csr_hw_reset 2.150s 1.135ms 5 5 100.00
V1 csr_rw adc_ctrl_csr_rw 2.080s 558.239us 20 20 100.00
V1 csr_bit_bash adc_ctrl_csr_bit_bash 1.663m 45.008ms 5 5 100.00
V1 csr_aliasing adc_ctrl_csr_aliasing 4.730s 1.113ms 5 5 100.00
V1 csr_mem_rw_with_rand_reset adc_ctrl_csr_mem_rw_with_rand_reset 2.510s 603.304us 20 20 100.00
V1 regwen_csr_and_corresponding_lockable_csr adc_ctrl_csr_rw 2.080s 558.239us 20 20 100.00
adc_ctrl_csr_aliasing 4.730s 1.113ms 5 5 100.00
V1 TOTAL 105 105 100.00
V2 filters_polled adc_ctrl_filters_polled 19.830m 495.873ms 50 50 100.00
V2 filters_polled_fixed adc_ctrl_filters_polled_fixed 20.110m 502.484ms 50 50 100.00
V2 filters_interrupt adc_ctrl_filters_interrupt 19.720m 482.890ms 50 50 100.00
V2 filters_interrupt_fixed adc_ctrl_filters_interrupt_fixed 19.857m 487.642ms 50 50 100.00
V2 filters_wakeup adc_ctrl_filters_wakeup 24.234m 624.764ms 50 50 100.00
V2 filters_wakeup_fixed adc_ctrl_filters_wakeup_fixed 24.307m 595.600ms 50 50 100.00
V2 filters_both adc_ctrl_filters_both 23.108m 565.677ms 50 50 100.00
V2 clock_gating adc_ctrl_clock_gating 21.953m 655.772ms 50 50 100.00
V2 poweron_counter adc_ctrl_poweron_counter 13.240s 4.904ms 50 50 100.00
V2 lowpower_counter adc_ctrl_lowpower_counter 1.719m 45.326ms 50 50 100.00
V2 fsm_reset adc_ctrl_fsm_reset 11.480m 130.561ms 50 50 100.00
V2 stress_all adc_ctrl_stress_all 35.474m 597.840ms 50 50 100.00
V2 alert_test adc_ctrl_alert_test 1.860s 532.993us 50 50 100.00
V2 intr_test adc_ctrl_intr_test 1.790s 525.688us 50 50 100.00
V2 tl_d_oob_addr_access adc_ctrl_tl_errors 3.810s 559.667us 20 20 100.00
V2 tl_d_illegal_access adc_ctrl_tl_errors 3.810s 559.667us 20 20 100.00
V2 tl_d_outstanding_access adc_ctrl_csr_hw_reset 2.150s 1.135ms 5 5 100.00
adc_ctrl_csr_rw 2.080s 558.239us 20 20 100.00
adc_ctrl_csr_aliasing 4.730s 1.113ms 5 5 100.00
adc_ctrl_same_csr_outstanding 16.580s 4.427ms 20 20 100.00
V2 tl_d_partial_access adc_ctrl_csr_hw_reset 2.150s 1.135ms 5 5 100.00
adc_ctrl_csr_rw 2.080s 558.239us 20 20 100.00
adc_ctrl_csr_aliasing 4.730s 1.113ms 5 5 100.00
adc_ctrl_same_csr_outstanding 16.580s 4.427ms 20 20 100.00
V2 TOTAL 740 740 100.00
V2S tl_intg_err adc_ctrl_sec_cm 11.210s 4.333ms 5 5 100.00
adc_ctrl_tl_intg_err 20.450s 8.059ms 20 20 100.00
V2S sec_cm_bus_integrity adc_ctrl_tl_intg_err 20.450s 8.059ms 20 20 100.00
V2S TOTAL 25 25 100.00
V3 stress_all_with_rand_reset adc_ctrl_stress_all_with_rand_reset 1.814m 1.120s 50 50 100.00
V3 TOTAL 50 50 100.00
TOTAL 920 920 100.00

Testplan Progress

Items Total Written Passing Progress
V1 6 6 6 100.00
V2 16 16 16 100.00
V2S 2 2 2 100.00
V3 1 1 1 100.00

Coverage Results

Coverage Dashboard

SCORE LINE COND TOGGLE FSM BRANCH ASSERT GROUP
97.68 99.07 96.67 100.00 100.00 98.83 98.33 90.84

Past Results