ADC_CTRL Simulation Results

Saturday August 17 2024 23:02:17 UTC

GitHub Revision: 76588857da

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 94235727392619910305578226901221990521512464990339520078429467885466612377995

Test Results

Stage Name Tests Max Job Runtime Simulated Time Passing Total Pass Rate
V1 smoke adc_ctrl_smoke 15.300s 5.755ms 50 50 100.00
V1 csr_hw_reset adc_ctrl_csr_hw_reset 1.680s 876.338us 5 5 100.00
V1 csr_rw adc_ctrl_csr_rw 2.080s 563.191us 20 20 100.00
V1 csr_bit_bash adc_ctrl_csr_bit_bash 2.959m 53.392ms 5 5 100.00
V1 csr_aliasing adc_ctrl_csr_aliasing 5.540s 1.215ms 5 5 100.00
V1 csr_mem_rw_with_rand_reset adc_ctrl_csr_mem_rw_with_rand_reset 2.070s 487.056us 20 20 100.00
V1 regwen_csr_and_corresponding_lockable_csr adc_ctrl_csr_rw 2.080s 563.191us 20 20 100.00
adc_ctrl_csr_aliasing 5.540s 1.215ms 5 5 100.00
V1 TOTAL 105 105 100.00
V2 filters_polled adc_ctrl_filters_polled 19.751m 487.647ms 50 50 100.00
V2 filters_polled_fixed adc_ctrl_filters_polled_fixed 20.008m 489.513ms 50 50 100.00
V2 filters_interrupt adc_ctrl_filters_interrupt 20.621m 492.684ms 50 50 100.00
V2 filters_interrupt_fixed adc_ctrl_filters_interrupt_fixed 20.025m 508.170ms 50 50 100.00
V2 filters_wakeup adc_ctrl_filters_wakeup 21.742m 572.145ms 50 50 100.00
V2 filters_wakeup_fixed adc_ctrl_filters_wakeup_fixed 24.833m 607.307ms 50 50 100.00
V2 filters_both adc_ctrl_filters_both 20.204m 532.110ms 50 50 100.00
V2 clock_gating adc_ctrl_clock_gating 21.384m 549.246ms 50 50 100.00
V2 poweron_counter adc_ctrl_poweron_counter 14.410s 5.323ms 50 50 100.00
V2 lowpower_counter adc_ctrl_lowpower_counter 1.742m 45.525ms 50 50 100.00
V2 fsm_reset adc_ctrl_fsm_reset 12.051m 141.666ms 50 50 100.00
V2 stress_all adc_ctrl_stress_all 27.114m 777.998ms 50 50 100.00
V2 alert_test adc_ctrl_alert_test 1.790s 491.207us 50 50 100.00
V2 intr_test adc_ctrl_intr_test 1.880s 476.548us 50 50 100.00
V2 tl_d_oob_addr_access adc_ctrl_tl_errors 3.460s 634.488us 20 20 100.00
V2 tl_d_illegal_access adc_ctrl_tl_errors 3.460s 634.488us 20 20 100.00
V2 tl_d_outstanding_access adc_ctrl_csr_hw_reset 1.680s 876.338us 5 5 100.00
adc_ctrl_csr_rw 2.080s 563.191us 20 20 100.00
adc_ctrl_csr_aliasing 5.540s 1.215ms 5 5 100.00
adc_ctrl_same_csr_outstanding 16.370s 4.514ms 20 20 100.00
V2 tl_d_partial_access adc_ctrl_csr_hw_reset 1.680s 876.338us 5 5 100.00
adc_ctrl_csr_rw 2.080s 563.191us 20 20 100.00
adc_ctrl_csr_aliasing 5.540s 1.215ms 5 5 100.00
adc_ctrl_same_csr_outstanding 16.370s 4.514ms 20 20 100.00
V2 TOTAL 740 740 100.00
V2S tl_intg_err adc_ctrl_sec_cm 10.410s 4.097ms 5 5 100.00
adc_ctrl_tl_intg_err 23.180s 8.368ms 20 20 100.00
V2S sec_cm_bus_integrity adc_ctrl_tl_intg_err 23.180s 8.368ms 20 20 100.00
V2S TOTAL 25 25 100.00
V3 stress_all_with_rand_reset adc_ctrl_stress_all_with_rand_reset 1.911m 3.243s 50 50 100.00
V3 TOTAL 50 50 100.00
TOTAL 920 920 100.00

Testplan Progress

Items Total Written Passing Progress
V1 6 6 6 100.00
V2 16 16 16 100.00
V2S 2 2 2 100.00
V3 1 1 1 100.00

Coverage Results

Coverage Dashboard

SCORE LINE COND TOGGLE FSM BRANCH ASSERT GROUP
97.77 99.07 96.67 100.00 100.00 98.83 98.33 91.51

Past Results