ADC_CTRL Simulation Results

Sunday August 18 2024 23:02:23 UTC

GitHub Revision: f1535c5540

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 29514139809134543525249635699831421949407409612590789671953066019961489233719

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	adc_ctrl_smoke	16.310s	5.767ms	50	50	100.00
V1	csr_hw_reset	adc_ctrl_csr_hw_reset	1.590s	1.384ms	5	5	100.00
V1	csr_rw	adc_ctrl_csr_rw	2.040s	548.414us	20	20	100.00
V1	csr_bit_bash	adc_ctrl_csr_bit_bash	2.059m	52.904ms	5	5	100.00
V1	csr_aliasing	adc_ctrl_csr_aliasing	3.390s	1.062ms	5	5	100.00
V1	csr_mem_rw_with_rand_reset	adc_ctrl_csr_mem_rw_with_rand_reset	2.520s	555.799us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	adc_ctrl_csr_rw	2.040s	548.414us	20	20	100.00
		adc_ctrl_csr_aliasing	3.390s	1.062ms	5	5	100.00
V1		TOTAL			105	105	100.00
V2	filters_polled	adc_ctrl_filters_polled	19.828m	502.759ms	50	50	100.00
V2	filters_polled_fixed	adc_ctrl_filters_polled_fixed	19.959m	499.889ms	50	50	100.00
V2	filters_interrupt	adc_ctrl_filters_interrupt	19.722m	499.440ms	50	50	100.00
V2	filters_interrupt_fixed	adc_ctrl_filters_interrupt_fixed	20.573m	491.134ms	50	50	100.00
V2	filters_wakeup	adc_ctrl_filters_wakeup	23.536m	568.212ms	50	50	100.00
V2	filters_wakeup_fixed	adc_ctrl_filters_wakeup_fixed	23.960m	603.451ms	50	50	100.00
V2	filters_both	adc_ctrl_filters_both	23.324m	600.000ms	49	50	98.00
V2	clock_gating	adc_ctrl_clock_gating	19.537m	514.427ms	50	50	100.00
V2	poweron_counter	adc_ctrl_poweron_counter	13.150s	4.836ms	50	50	100.00
V2	lowpower_counter	adc_ctrl_lowpower_counter	1.695m	46.381ms	50	50	100.00
V2	fsm_reset	adc_ctrl_fsm_reset	12.504m	144.903ms	50	50	100.00
V2	stress_all	adc_ctrl_stress_all	38.274m	924.829ms	50	50	100.00
V2	alert_test	adc_ctrl_alert_test	1.870s	520.789us	50	50	100.00
V2	intr_test	adc_ctrl_intr_test	1.920s	512.683us	50	50	100.00
V2	tl_d_oob_addr_access	adc_ctrl_tl_errors	3.500s	1.111ms	20	20	100.00
V2	tl_d_illegal_access	adc_ctrl_tl_errors	3.500s	1.111ms	20	20	100.00
V2	tl_d_outstanding_access	adc_ctrl_csr_hw_reset	1.590s	1.384ms	5	5	100.00
		adc_ctrl_csr_rw	2.040s	548.414us	20	20	100.00
		adc_ctrl_csr_aliasing	3.390s	1.062ms	5	5	100.00
		adc_ctrl_same_csr_outstanding	19.380s	4.916ms	20	20	100.00
V2	tl_d_partial_access	adc_ctrl_csr_hw_reset	1.590s	1.384ms	5	5	100.00
		adc_ctrl_csr_rw	2.040s	548.414us	20	20	100.00
		adc_ctrl_csr_aliasing	3.390s	1.062ms	5	5	100.00
		adc_ctrl_same_csr_outstanding	19.380s	4.916ms	20	20	100.00
V2		TOTAL			739	740	99.86
V2S	tl_intg_err	adc_ctrl_sec_cm	18.980s	7.642ms	5	5	100.00
		adc_ctrl_tl_intg_err	20.660s	8.159ms	20	20	100.00
V2S	sec_cm_bus_integrity	adc_ctrl_tl_intg_err	20.660s	8.159ms	20	20	100.00
V2S		TOTAL			25	25	100.00
V3	stress_all_with_rand_reset	adc_ctrl_stress_all_with_rand_reset	45.880s	22.364ms	50	50	100.00
V3		TOTAL			50	50	100.00
		TOTAL			919	920	99.89

Testplan Progress

Items	Total	Written	Passing	Progress
V1	6	6	6	100.00
V2	16	16	15	93.75
V2S	2	2	2	100.00
V3	1	1	1	100.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
97.69	99.07	96.67	100.00	100.00	98.83	98.33	90.97

Failure Buckets

• UVM_FATAL (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue has 1 failures:
  • Test adc_ctrl_filters_both has 1 failures.

    • 3.adc_ctrl_filters_both.19795754217135058866941711905883691186019023861854416057680579572952873623038
      Line 357, in log /container/opentitan-public/scratch/os_regression/adc_ctrl-sim-vcs/3.adc_ctrl_filters_both/latest/run.log

        UVM_FATAL @ 600000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 600000000000 ps hit, indicating a probable testbench issue
        UVM_INFO @ 600000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

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