ADC_CTRL Simulation Results

Monday August 19 2024 23:02:17 UTC

GitHub Revision: e45ccd274a

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 28901767565311589526059483176077826609560752276120463932311122284088110669824

Test Results

Stage Name Tests Max Job Runtime Simulated Time Passing Total Pass Rate
V1 smoke adc_ctrl_smoke 16.110s 5.913ms 50 50 100.00
V1 csr_hw_reset adc_ctrl_csr_hw_reset 2.450s 780.206us 5 5 100.00
V1 csr_rw adc_ctrl_csr_rw 1.920s 528.625us 20 20 100.00
V1 csr_bit_bash adc_ctrl_csr_bit_bash 2.543m 38.519ms 5 5 100.00
V1 csr_aliasing adc_ctrl_csr_aliasing 4.020s 768.229us 5 5 100.00
V1 csr_mem_rw_with_rand_reset adc_ctrl_csr_mem_rw_with_rand_reset 2.270s 478.637us 20 20 100.00
V1 regwen_csr_and_corresponding_lockable_csr adc_ctrl_csr_rw 1.920s 528.625us 20 20 100.00
adc_ctrl_csr_aliasing 4.020s 768.229us 5 5 100.00
V1 TOTAL 105 105 100.00
V2 filters_polled adc_ctrl_filters_polled 19.776m 486.395ms 50 50 100.00
V2 filters_polled_fixed adc_ctrl_filters_polled_fixed 19.967m 487.339ms 50 50 100.00
V2 filters_interrupt adc_ctrl_filters_interrupt 19.397m 483.384ms 50 50 100.00
V2 filters_interrupt_fixed adc_ctrl_filters_interrupt_fixed 20.464m 497.201ms 50 50 100.00
V2 filters_wakeup adc_ctrl_filters_wakeup 24.044m 624.233ms 50 50 100.00
V2 filters_wakeup_fixed adc_ctrl_filters_wakeup_fixed 23.920m 603.069ms 50 50 100.00
V2 filters_both adc_ctrl_filters_both 22.387m 552.895ms 50 50 100.00
V2 clock_gating adc_ctrl_clock_gating 20.608m 541.273ms 50 50 100.00
V2 poweron_counter adc_ctrl_poweron_counter 11.640s 4.660ms 50 50 100.00
V2 lowpower_counter adc_ctrl_lowpower_counter 1.853m 47.156ms 50 50 100.00
V2 fsm_reset adc_ctrl_fsm_reset 11.859m 128.015ms 50 50 100.00
V2 stress_all adc_ctrl_stress_all 22.368m 413.572ms 50 50 100.00
V2 alert_test adc_ctrl_alert_test 1.800s 520.540us 50 50 100.00
V2 intr_test adc_ctrl_intr_test 1.930s 526.844us 50 50 100.00
V2 tl_d_oob_addr_access adc_ctrl_tl_errors 3.630s 638.617us 20 20 100.00
V2 tl_d_illegal_access adc_ctrl_tl_errors 3.630s 638.617us 20 20 100.00
V2 tl_d_outstanding_access adc_ctrl_csr_hw_reset 2.450s 780.206us 5 5 100.00
adc_ctrl_csr_rw 1.920s 528.625us 20 20 100.00
adc_ctrl_csr_aliasing 4.020s 768.229us 5 5 100.00
adc_ctrl_same_csr_outstanding 16.760s 4.412ms 20 20 100.00
V2 tl_d_partial_access adc_ctrl_csr_hw_reset 2.450s 780.206us 5 5 100.00
adc_ctrl_csr_rw 1.920s 528.625us 20 20 100.00
adc_ctrl_csr_aliasing 4.020s 768.229us 5 5 100.00
adc_ctrl_same_csr_outstanding 16.760s 4.412ms 20 20 100.00
V2 TOTAL 740 740 100.00
V2S tl_intg_err adc_ctrl_sec_cm 16.940s 7.542ms 5 5 100.00
adc_ctrl_tl_intg_err 22.210s 8.343ms 20 20 100.00
V2S sec_cm_bus_integrity adc_ctrl_tl_intg_err 22.210s 8.343ms 20 20 100.00
V2S TOTAL 25 25 100.00
V3 stress_all_with_rand_reset adc_ctrl_stress_all_with_rand_reset 27.940s 710.330ms 50 50 100.00
V3 TOTAL 50 50 100.00
TOTAL 920 920 100.00

Testplan Progress

Items Total Written Passing Progress
V1 6 6 6 100.00
V2 16 16 16 100.00
V2S 2 2 2 100.00
V3 1 1 1 100.00

Coverage Results

Coverage Dashboard

SCORE LINE COND TOGGLE FSM BRANCH ASSERT GROUP
97.75 99.07 96.67 100.00 100.00 98.83 98.33 91.34

Past Results