ADC_CTRL Simulation Results

Wednesday August 21 2024 01:12:47 UTC

GitHub Revision: 34b8fc33e3

Branch: earlgrey_1_0_0_2024_08_20_RC0

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 77645589415139663032322841827996135987237190720163469870959218015679941996572

Test Results

Stage Name Tests Max Job Runtime Simulated Time Passing Total Pass Rate
V1 smoke adc_ctrl_smoke 26.920s 6.093ms 50 50 100.00
V1 csr_hw_reset adc_ctrl_csr_hw_reset 4.300s 778.769us 5 5 100.00
V1 csr_rw adc_ctrl_csr_rw 2.950s 438.127us 20 20 100.00
V1 csr_bit_bash adc_ctrl_csr_bit_bash 1.847m 26.160ms 5 5 100.00
V1 csr_aliasing adc_ctrl_csr_aliasing 8.340s 1.209ms 5 5 100.00
V1 csr_mem_rw_with_rand_reset adc_ctrl_csr_mem_rw_with_rand_reset 3.650s 535.110us 20 20 100.00
V1 regwen_csr_and_corresponding_lockable_csr adc_ctrl_csr_rw 2.950s 438.127us 20 20 100.00
adc_ctrl_csr_aliasing 8.340s 1.209ms 5 5 100.00
V1 TOTAL 105 105 100.00
V2 filters_polled adc_ctrl_filters_polled 25.746m 499.655ms 50 50 100.00
V2 filters_polled_fixed adc_ctrl_filters_polled_fixed 26.274m 495.158ms 50 50 100.00
V2 filters_interrupt adc_ctrl_filters_interrupt 27.902m 497.695ms 50 50 100.00
V2 filters_interrupt_fixed adc_ctrl_filters_interrupt_fixed 24.576m 497.311ms 50 50 100.00
V2 filters_wakeup adc_ctrl_filters_wakeup 26.053m 535.690ms 50 50 100.00
V2 filters_wakeup_fixed adc_ctrl_filters_wakeup_fixed 32.954m 620.364ms 50 50 100.00
V2 filters_both adc_ctrl_filters_both 30.307m 593.376ms 50 50 100.00
V2 clock_gating adc_ctrl_clock_gating 27.961m 562.440ms 50 50 100.00
V2 poweron_counter adc_ctrl_poweron_counter 24.710s 5.390ms 50 50 100.00
V2 lowpower_counter adc_ctrl_lowpower_counter 3.305m 45.135ms 50 50 100.00
V2 fsm_reset adc_ctrl_fsm_reset 15.689m 143.496ms 50 50 100.00
V2 stress_all adc_ctrl_stress_all 28.247m 481.761ms 50 50 100.00
V2 alert_test adc_ctrl_alert_test 3.030s 494.128us 50 50 100.00
V2 intr_test adc_ctrl_intr_test 3.030s 510.957us 50 50 100.00
V2 tl_d_oob_addr_access adc_ctrl_tl_errors 4.800s 412.562us 20 20 100.00
V2 tl_d_illegal_access adc_ctrl_tl_errors 4.800s 412.562us 20 20 100.00
V2 tl_d_outstanding_access adc_ctrl_csr_hw_reset 4.300s 778.769us 5 5 100.00
adc_ctrl_csr_rw 2.950s 438.127us 20 20 100.00
adc_ctrl_csr_aliasing 8.340s 1.209ms 5 5 100.00
adc_ctrl_same_csr_outstanding 17.840s 4.940ms 20 20 100.00
V2 tl_d_partial_access adc_ctrl_csr_hw_reset 4.300s 778.769us 5 5 100.00
adc_ctrl_csr_rw 2.950s 438.127us 20 20 100.00
adc_ctrl_csr_aliasing 8.340s 1.209ms 5 5 100.00
adc_ctrl_same_csr_outstanding 17.840s 4.940ms 20 20 100.00
V2 TOTAL 740 740 100.00
V2S tl_intg_err adc_ctrl_sec_cm 22.050s 7.582ms 5 5 100.00
adc_ctrl_tl_intg_err 35.930s 8.313ms 20 20 100.00
V2S sec_cm_bus_integrity adc_ctrl_tl_intg_err 35.930s 8.313ms 20 20 100.00
V2S TOTAL 25 25 100.00
V3 stress_all_with_rand_reset adc_ctrl_stress_all_with_rand_reset 45.870s 14.437ms 50 50 100.00
V3 TOTAL 50 50 100.00
TOTAL 920 920 100.00

Testplan Progress

Items Total Written Passing Progress
V1 6 6 6 100.00
V2 16 16 16 100.00
V2S 2 2 2 100.00
V3 1 1 1 100.00

Coverage Results

Coverage Dashboard

SCORE LINE COND TOGGLE FSM BRANCH ASSERT GROUP
97.56 99.07 96.67 100.00 100.00 98.83 98.33 90.04

Past Results