ADC_CTRL Simulation Results

Thursday August 22 2024 22:02:20 UTC

GitHub Revision: 0825c81be0

Branch: os_regression_2024_08_22

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 102736032995262985039236458937944411119924968439319752111682827040046827694889

Test Results

Stage Name Tests Max Job Runtime Simulated Time Passing Total Pass Rate
V1 smoke adc_ctrl_smoke 15.650s 6.062ms 50 50 100.00
V1 csr_hw_reset adc_ctrl_csr_hw_reset 3.120s 1.242ms 5 5 100.00
V1 csr_rw adc_ctrl_csr_rw 1.650s 488.530us 20 20 100.00
V1 csr_bit_bash adc_ctrl_csr_bit_bash 1.400m 34.983ms 5 5 100.00
V1 csr_aliasing adc_ctrl_csr_aliasing 4.990s 1.201ms 5 5 100.00
V1 csr_mem_rw_with_rand_reset adc_ctrl_csr_mem_rw_with_rand_reset 1.920s 403.263us 20 20 100.00
V1 regwen_csr_and_corresponding_lockable_csr adc_ctrl_csr_rw 1.650s 488.530us 20 20 100.00
adc_ctrl_csr_aliasing 4.990s 1.201ms 5 5 100.00
V1 TOTAL 105 105 100.00
V2 filters_polled adc_ctrl_filters_polled 19.650m 501.191ms 50 50 100.00
V2 filters_polled_fixed adc_ctrl_filters_polled_fixed 18.018m 487.255ms 50 50 100.00
V2 filters_interrupt adc_ctrl_filters_interrupt 18.064m 498.010ms 50 50 100.00
V2 filters_interrupt_fixed adc_ctrl_filters_interrupt_fixed 17.988m 487.969ms 50 50 100.00
V2 filters_wakeup adc_ctrl_filters_wakeup 21.633m 615.925ms 50 50 100.00
V2 filters_wakeup_fixed adc_ctrl_filters_wakeup_fixed 24.210m 629.543ms 50 50 100.00
V2 filters_both adc_ctrl_filters_both 20.287m 534.164ms 50 50 100.00
V2 clock_gating adc_ctrl_clock_gating 16.916m 523.315ms 50 50 100.00
V2 poweron_counter adc_ctrl_poweron_counter 12.970s 5.320ms 50 50 100.00
V2 lowpower_counter adc_ctrl_lowpower_counter 1.701m 45.529ms 50 50 100.00
V2 fsm_reset adc_ctrl_fsm_reset 11.666m 143.927ms 50 50 100.00
V2 stress_all adc_ctrl_stress_all 26.931m 605.600ms 50 50 100.00
V2 alert_test adc_ctrl_alert_test 1.750s 480.453us 50 50 100.00
V2 intr_test adc_ctrl_intr_test 1.630s 466.265us 50 50 100.00
V2 tl_d_oob_addr_access adc_ctrl_tl_errors 2.950s 529.399us 20 20 100.00
V2 tl_d_illegal_access adc_ctrl_tl_errors 2.950s 529.399us 20 20 100.00
V2 tl_d_outstanding_access adc_ctrl_csr_hw_reset 3.120s 1.242ms 5 5 100.00
adc_ctrl_csr_rw 1.650s 488.530us 20 20 100.00
adc_ctrl_csr_aliasing 4.990s 1.201ms 5 5 100.00
adc_ctrl_same_csr_outstanding 9.250s 4.595ms 20 20 100.00
V2 tl_d_partial_access adc_ctrl_csr_hw_reset 3.120s 1.242ms 5 5 100.00
adc_ctrl_csr_rw 1.650s 488.530us 20 20 100.00
adc_ctrl_csr_aliasing 4.990s 1.201ms 5 5 100.00
adc_ctrl_same_csr_outstanding 9.250s 4.595ms 20 20 100.00
V2 TOTAL 740 740 100.00
V2S tl_intg_err adc_ctrl_sec_cm 17.790s 8.205ms 5 5 100.00
adc_ctrl_tl_intg_err 19.920s 8.631ms 20 20 100.00
V2S sec_cm_bus_integrity adc_ctrl_tl_intg_err 19.920s 8.631ms 20 20 100.00
V2S TOTAL 25 25 100.00
V3 stress_all_with_rand_reset adc_ctrl_stress_all_with_rand_reset 53.050s 63.232ms 50 50 100.00
V3 TOTAL 50 50 100.00
TOTAL 920 920 100.00

Testplan Progress

Items Total Written Passing Progress
V1 6 6 6 100.00
V2 16 16 16 100.00
V2S 2 2 2 100.00
V3 1 1 1 100.00

Coverage Results

Coverage Dashboard

SCORE LINE COND TOGGLE FSM BRANCH ASSERT GROUP
97.71 99.07 96.67 100.00 100.00 98.83 98.33 91.07

Past Results