ADC_CTRL Simulation Results

Saturday August 24 2024 20:58:08 UTC

GitHub Revision: e733a8ef8a

Branch: os_regression_2024_08_24

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 36240513409906943553650221581975102764006655953510936167454320581301243659163

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	adc_ctrl_smoke	30.050s	5.918ms	50	50	100.00
V1	csr_hw_reset	adc_ctrl_csr_hw_reset	6.560s	1.168ms	5	5	100.00
V1	csr_rw	adc_ctrl_csr_rw	3.430s	540.607us	20	20	100.00
V1	csr_bit_bash	adc_ctrl_csr_bit_bash	3.536m	52.437ms	5	5	100.00
V1	csr_aliasing	adc_ctrl_csr_aliasing	5.120s	1.096ms	5	5	100.00
V1	csr_mem_rw_with_rand_reset	adc_ctrl_csr_mem_rw_with_rand_reset	3.580s	499.064us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	adc_ctrl_csr_rw	3.430s	540.607us	20	20	100.00
		adc_ctrl_csr_aliasing	5.120s	1.096ms	5	5	100.00
V1		TOTAL			105	105	100.00
V2	filters_polled	adc_ctrl_filters_polled	33.541m	488.361ms	50	50	100.00
V2	filters_polled_fixed	adc_ctrl_filters_polled_fixed	36.542m	481.404ms	50	50	100.00
V2	filters_interrupt	adc_ctrl_filters_interrupt	33.817m	494.350ms	50	50	100.00
V2	filters_interrupt_fixed	adc_ctrl_filters_interrupt_fixed	24.281m	332.394ms	50	50	100.00
V2	filters_wakeup	adc_ctrl_filters_wakeup	27.168m	403.318ms	50	50	100.00
V2	filters_wakeup_fixed	adc_ctrl_filters_wakeup_fixed	46.847m	601.667ms	50	50	100.00
V2	filters_both	adc_ctrl_filters_both	37.373m	596.079ms	50	50	100.00
V2	clock_gating	adc_ctrl_clock_gating	34.548m	509.436ms	50	50	100.00
V2	poweron_counter	adc_ctrl_poweron_counter	24.810s	5.488ms	50	50	100.00
V2	lowpower_counter	adc_ctrl_lowpower_counter	3.313m	46.839ms	50	50	100.00
V2	fsm_reset	adc_ctrl_fsm_reset	21.689m	142.814ms	50	50	100.00
V2	stress_all	adc_ctrl_stress_all	54.278m	755.485ms	50	50	100.00
V2	alert_test	adc_ctrl_alert_test	3.110s	481.077us	50	50	100.00
V2	intr_test	adc_ctrl_intr_test	3.200s	523.087us	50	50	100.00
V2	tl_d_oob_addr_access	adc_ctrl_tl_errors	5.560s	494.116us	20	20	100.00
V2	tl_d_illegal_access	adc_ctrl_tl_errors	5.560s	494.116us	20	20	100.00
V2	tl_d_outstanding_access	adc_ctrl_csr_hw_reset	6.560s	1.168ms	5	5	100.00
		adc_ctrl_csr_rw	3.430s	540.607us	20	20	100.00
		adc_ctrl_csr_aliasing	5.120s	1.096ms	5	5	100.00
		adc_ctrl_same_csr_outstanding	31.720s	4.529ms	20	20	100.00
V2	tl_d_partial_access	adc_ctrl_csr_hw_reset	6.560s	1.168ms	5	5	100.00
		adc_ctrl_csr_rw	3.430s	540.607us	20	20	100.00
		adc_ctrl_csr_aliasing	5.120s	1.096ms	5	5	100.00
		adc_ctrl_same_csr_outstanding	31.720s	4.529ms	20	20	100.00
V2		TOTAL			740	740	100.00
V2S	tl_intg_err	adc_ctrl_sec_cm	41.850s	8.496ms	5	5	100.00
		adc_ctrl_tl_intg_err	39.460s	8.478ms	20	20	100.00
V2S	sec_cm_bus_integrity	adc_ctrl_tl_intg_err	39.460s	8.478ms	20	20	100.00
V2S		TOTAL			25	25	100.00
V3	stress_all_with_rand_reset	adc_ctrl_stress_all_with_rand_reset	1.932m	97.185ms	49	50	98.00
V3		TOTAL			49	50	98.00
		TOTAL			919	920	99.89

Testplan Progress

Items	Total	Written	Passing	Progress
V1	6	6	6	100.00
V2	16	16	16	100.00
V2S	2	2	2	100.00
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
97.70	99.07	96.67	100.00	100.00	98.83	98.33	91.02

Failure Buckets

• Offending '(np_sample_cnt_q == '0)' has 1 failures:
  • Test adc_ctrl_stress_all_with_rand_reset has 1 failures.

    • 21.adc_ctrl_stress_all_with_rand_reset.50088495074669600344419191598281544382293048140707692838645021955539896240768
      Line 226, in log /workspaces/repo/scratch/os_regression_2024_08_24/adc_ctrl-sim-vcs/21.adc_ctrl_stress_all_with_rand_reset/latest/run.log

            Offending '(np_sample_cnt_q == '0)'
        UVM_ERROR @ 9813981405 ps: (adc_ctrl_fsm.sv:384) [ASSERT FAILED] NpCntClrPwrDn_A
        UVM_INFO @ 9813981405 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

Past Results

• Latest
• lint
• 2024.08.24_19.53.35
• 2024.08.22_13.55.22
• 2024.08.20_07.40.12
• 2024.08.19_07.54.26
• 2024.08.18_08.24.14
• 2024.08.17_07.00.18