ADC_CTRL Simulation Results

Monday August 26 2024 23:33:20 UTC

GitHub Revision: 4674f625b3

Branch: os_regression_2024_08_26

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 27137705585251537962012108482438895412147493342955425380690984800523869492310

Test Results

Stage Name Tests Max Job Runtime Simulated Time Passing Total Pass Rate
V1 smoke adc_ctrl_smoke 27.440s 6.152ms 50 50 100.00
V1 csr_hw_reset adc_ctrl_csr_hw_reset 5.690s 940.883us 5 5 100.00
V1 csr_rw adc_ctrl_csr_rw 3.950s 523.331us 20 20 100.00
V1 csr_bit_bash adc_ctrl_csr_bit_bash 1.518m 26.625ms 5 5 100.00
V1 csr_aliasing adc_ctrl_csr_aliasing 11.120s 1.407ms 5 5 100.00
V1 csr_mem_rw_with_rand_reset adc_ctrl_csr_mem_rw_with_rand_reset 3.970s 581.236us 20 20 100.00
V1 regwen_csr_and_corresponding_lockable_csr adc_ctrl_csr_rw 3.950s 523.331us 20 20 100.00
adc_ctrl_csr_aliasing 11.120s 1.407ms 5 5 100.00
V1 TOTAL 105 105 100.00
V2 filters_polled adc_ctrl_filters_polled 25.220m 489.809ms 50 50 100.00
V2 filters_polled_fixed adc_ctrl_filters_polled_fixed 25.122m 497.637ms 50 50 100.00
V2 filters_interrupt adc_ctrl_filters_interrupt 23.179m 499.008ms 50 50 100.00
V2 filters_interrupt_fixed adc_ctrl_filters_interrupt_fixed 23.452m 489.316ms 50 50 100.00
V2 filters_wakeup adc_ctrl_filters_wakeup 26.818m 581.742ms 50 50 100.00
V2 filters_wakeup_fixed adc_ctrl_filters_wakeup_fixed 29.373m 615.197ms 50 50 100.00
V2 filters_both adc_ctrl_filters_both 26.595m 510.000ms 50 50 100.00
V2 clock_gating adc_ctrl_clock_gating 28.198m 503.161ms 50 50 100.00
V2 poweron_counter adc_ctrl_poweron_counter 21.260s 4.841ms 50 50 100.00
V2 lowpower_counter adc_ctrl_lowpower_counter 2.686m 41.636ms 50 50 100.00
V2 fsm_reset adc_ctrl_fsm_reset 15.523m 125.774ms 50 50 100.00
V2 stress_all adc_ctrl_stress_all 1.405h 1.680s 50 50 100.00
V2 alert_test adc_ctrl_alert_test 2.990s 505.356us 50 50 100.00
V2 intr_test adc_ctrl_intr_test 3.630s 505.126us 50 50 100.00
V2 tl_d_oob_addr_access adc_ctrl_tl_errors 5.460s 513.009us 20 20 100.00
V2 tl_d_illegal_access adc_ctrl_tl_errors 5.460s 513.009us 20 20 100.00
V2 tl_d_outstanding_access adc_ctrl_csr_hw_reset 5.690s 940.883us 5 5 100.00
adc_ctrl_csr_rw 3.950s 523.331us 20 20 100.00
adc_ctrl_csr_aliasing 11.120s 1.407ms 5 5 100.00
adc_ctrl_same_csr_outstanding 29.670s 4.589ms 20 20 100.00
V2 tl_d_partial_access adc_ctrl_csr_hw_reset 5.690s 940.883us 5 5 100.00
adc_ctrl_csr_rw 3.950s 523.331us 20 20 100.00
adc_ctrl_csr_aliasing 11.120s 1.407ms 5 5 100.00
adc_ctrl_same_csr_outstanding 29.670s 4.589ms 20 20 100.00
V2 TOTAL 740 740 100.00
V2S tl_intg_err adc_ctrl_sec_cm 22.260s 8.010ms 5 5 100.00
adc_ctrl_tl_intg_err 45.780s 8.422ms 20 20 100.00
V2S sec_cm_bus_integrity adc_ctrl_tl_intg_err 45.780s 8.422ms 20 20 100.00
V2S TOTAL 25 25 100.00
V3 stress_all_with_rand_reset adc_ctrl_stress_all_with_rand_reset 1.086m 170.912ms 50 50 100.00
V3 TOTAL 50 50 100.00
TOTAL 920 920 100.00

Testplan Progress

Items Total Written Passing Progress
V1 6 6 6 100.00
V2 16 16 16 100.00
V2S 2 2 2 100.00
V3 1 1 1 100.00

Coverage Results

Coverage Dashboard

SCORE LINE COND TOGGLE FSM BRANCH ASSERT GROUP
97.73 99.07 96.67 100.00 100.00 98.83 98.33 91.24

Past Results