ADC_CTRL Simulation Results

Wednesday August 28 2024 16:26:26 UTC

GitHub Revision: a861deb3de

Branch: os_regression_2024_08_28

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 1071354200461384473511155521960728188378582408849032283874664554749864050652

Test Results

Stage Name Tests Max Job Runtime Simulated Time Passing Total Pass Rate
V1 smoke adc_ctrl_smoke 27.400s 5.742ms 50 50 100.00
V1 csr_hw_reset adc_ctrl_csr_hw_reset 6.790s 1.206ms 5 5 100.00
V1 csr_rw adc_ctrl_csr_rw 3.420s 537.116us 20 20 100.00
V1 csr_bit_bash adc_ctrl_csr_bit_bash 3.151m 26.990ms 5 5 100.00
V1 csr_aliasing adc_ctrl_csr_aliasing 7.300s 1.153ms 5 5 100.00
V1 csr_mem_rw_with_rand_reset adc_ctrl_csr_mem_rw_with_rand_reset 3.710s 522.378us 20 20 100.00
V1 regwen_csr_and_corresponding_lockable_csr adc_ctrl_csr_rw 3.420s 537.116us 20 20 100.00
adc_ctrl_csr_aliasing 7.300s 1.153ms 5 5 100.00
V1 TOTAL 105 105 100.00
V2 filters_polled adc_ctrl_filters_polled 27.170m 482.352ms 50 50 100.00
V2 filters_polled_fixed adc_ctrl_filters_polled_fixed 27.559m 486.185ms 50 50 100.00
V2 filters_interrupt adc_ctrl_filters_interrupt 24.713m 485.463ms 50 50 100.00
V2 filters_interrupt_fixed adc_ctrl_filters_interrupt_fixed 25.993m 500.640ms 50 50 100.00
V2 filters_wakeup adc_ctrl_filters_wakeup 35.360m 554.979ms 50 50 100.00
V2 filters_wakeup_fixed adc_ctrl_filters_wakeup_fixed 32.961m 598.092ms 50 50 100.00
V2 filters_both adc_ctrl_filters_both 27.469m 508.492ms 49 50 98.00
V2 clock_gating adc_ctrl_clock_gating 25.025m 557.627ms 50 50 100.00
V2 poweron_counter adc_ctrl_poweron_counter 23.730s 5.297ms 50 50 100.00
V2 lowpower_counter adc_ctrl_lowpower_counter 2.957m 44.134ms 50 50 100.00
V2 fsm_reset adc_ctrl_fsm_reset 16.533m 120.853ms 50 50 100.00
V2 stress_all adc_ctrl_stress_all 1.578h 1.848s 50 50 100.00
V2 alert_test adc_ctrl_alert_test 3.060s 510.753us 50 50 100.00
V2 intr_test adc_ctrl_intr_test 3.320s 508.808us 50 50 100.00
V2 tl_d_oob_addr_access adc_ctrl_tl_errors 5.310s 437.656us 20 20 100.00
V2 tl_d_illegal_access adc_ctrl_tl_errors 5.310s 437.656us 20 20 100.00
V2 tl_d_outstanding_access adc_ctrl_csr_hw_reset 6.790s 1.206ms 5 5 100.00
adc_ctrl_csr_rw 3.420s 537.116us 20 20 100.00
adc_ctrl_csr_aliasing 7.300s 1.153ms 5 5 100.00
adc_ctrl_same_csr_outstanding 18.920s 2.745ms 20 20 100.00
V2 tl_d_partial_access adc_ctrl_csr_hw_reset 6.790s 1.206ms 5 5 100.00
adc_ctrl_csr_rw 3.420s 537.116us 20 20 100.00
adc_ctrl_csr_aliasing 7.300s 1.153ms 5 5 100.00
adc_ctrl_same_csr_outstanding 18.920s 2.745ms 20 20 100.00
V2 TOTAL 739 740 99.86
V2S tl_intg_err adc_ctrl_sec_cm 32.630s 8.146ms 5 5 100.00
adc_ctrl_tl_intg_err 32.770s 8.793ms 20 20 100.00
V2S sec_cm_bus_integrity adc_ctrl_tl_intg_err 32.770s 8.793ms 20 20 100.00
V2S TOTAL 25 25 100.00
V3 stress_all_with_rand_reset adc_ctrl_stress_all_with_rand_reset 1.390m 911.269ms 50 50 100.00
V3 TOTAL 50 50 100.00
TOTAL 919 920 99.89

Testplan Progress

Items Total Written Passing Progress
V1 6 6 6 100.00
V2 16 16 15 93.75
V2S 2 2 2 100.00
V3 1 1 1 100.00

Coverage Results

Coverage Dashboard

SCORE LINE COND TOGGLE FSM BRANCH ASSERT GROUP
97.76 99.07 96.67 100.00 100.00 98.83 98.33 91.42

Failure Buckets

Past Results