ADC_CTRL Simulation Results

Sunday September 01 2024 02:56:32 UTC

GitHub Revision: ed1c41cd0f

Branch: os_regression_2024_08_31

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 79046303479535931055412478968949166876277637335647713094117953182855865639399

Test Results

Stage Name Tests Max Job Runtime Simulated Time Passing Total Pass Rate
V1 smoke adc_ctrl_smoke 26.190s 5.742ms 50 50 100.00
V1 csr_hw_reset adc_ctrl_csr_hw_reset 6.200s 1.283ms 5 5 100.00
V1 csr_rw adc_ctrl_csr_rw 2.900s 490.296us 20 20 100.00
V1 csr_bit_bash adc_ctrl_csr_bit_bash 2.543m 53.837ms 5 5 100.00
V1 csr_aliasing adc_ctrl_csr_aliasing 6.710s 1.205ms 5 5 100.00
V1 csr_mem_rw_with_rand_reset adc_ctrl_csr_mem_rw_with_rand_reset 3.860s 601.870us 20 20 100.00
V1 regwen_csr_and_corresponding_lockable_csr adc_ctrl_csr_rw 2.900s 490.296us 20 20 100.00
adc_ctrl_csr_aliasing 6.710s 1.205ms 5 5 100.00
V1 TOTAL 105 105 100.00
V2 filters_polled adc_ctrl_filters_polled 27.292m 487.488ms 50 50 100.00
V2 filters_polled_fixed adc_ctrl_filters_polled_fixed 28.210m 494.894ms 50 50 100.00
V2 filters_interrupt adc_ctrl_filters_interrupt 27.888m 497.199ms 50 50 100.00
V2 filters_interrupt_fixed adc_ctrl_filters_interrupt_fixed 27.234m 497.745ms 50 50 100.00
V2 filters_wakeup adc_ctrl_filters_wakeup 31.091m 517.586ms 50 50 100.00
V2 filters_wakeup_fixed adc_ctrl_filters_wakeup_fixed 33.294m 601.216ms 50 50 100.00
V2 filters_both adc_ctrl_filters_both 27.696m 540.402ms 50 50 100.00
V2 clock_gating adc_ctrl_clock_gating 29.012m 581.840ms 50 50 100.00
V2 poweron_counter adc_ctrl_poweron_counter 23.180s 4.307ms 50 50 100.00
V2 lowpower_counter adc_ctrl_lowpower_counter 3.446m 48.184ms 50 50 100.00
V2 fsm_reset adc_ctrl_fsm_reset 15.820m 123.704ms 50 50 100.00
V2 stress_all adc_ctrl_stress_all 38.306m 430.294ms 50 50 100.00
V2 alert_test adc_ctrl_alert_test 3.130s 520.419us 50 50 100.00
V2 intr_test adc_ctrl_intr_test 3.160s 522.071us 50 50 100.00
V2 tl_d_oob_addr_access adc_ctrl_tl_errors 5.770s 511.465us 20 20 100.00
V2 tl_d_illegal_access adc_ctrl_tl_errors 5.770s 511.465us 20 20 100.00
V2 tl_d_outstanding_access adc_ctrl_csr_hw_reset 6.200s 1.283ms 5 5 100.00
adc_ctrl_csr_rw 2.900s 490.296us 20 20 100.00
adc_ctrl_csr_aliasing 6.710s 1.205ms 5 5 100.00
adc_ctrl_same_csr_outstanding 22.480s 4.384ms 20 20 100.00
V2 tl_d_partial_access adc_ctrl_csr_hw_reset 6.200s 1.283ms 5 5 100.00
adc_ctrl_csr_rw 2.900s 490.296us 20 20 100.00
adc_ctrl_csr_aliasing 6.710s 1.205ms 5 5 100.00
adc_ctrl_same_csr_outstanding 22.480s 4.384ms 20 20 100.00
V2 TOTAL 740 740 100.00
V2S tl_intg_err adc_ctrl_sec_cm 31.170s 8.183ms 5 5 100.00
adc_ctrl_tl_intg_err 33.630s 8.631ms 20 20 100.00
V2S sec_cm_bus_integrity adc_ctrl_tl_intg_err 33.630s 8.631ms 20 20 100.00
V2S TOTAL 25 25 100.00
V3 stress_all_with_rand_reset adc_ctrl_stress_all_with_rand_reset 1.317m 62.833ms 50 50 100.00
V3 TOTAL 50 50 100.00
TOTAL 920 920 100.00

Testplan Progress

Items Total Written Passing Progress
V1 6 6 6 100.00
V2 16 16 16 100.00
V2S 2 2 2 100.00
V3 1 1 1 100.00

Coverage Results

Coverage Dashboard

SCORE LINE COND TOGGLE FSM BRANCH ASSERT GROUP
97.71 99.07 96.67 100.00 100.00 98.83 98.33 91.09

Past Results