ADC_CTRL Simulation Results

Tuesday September 03 2024 20:34:49 UTC

GitHub Revision: 372a6306e0

Branch: os_regression_2024_09_03

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 13282233770562214583722256565474794620746865855733889385758507057043002787586

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	adc_ctrl_smoke	32.410s	5.853ms	50	50	100.00
V1	csr_hw_reset	adc_ctrl_csr_hw_reset	5.900s	1.059ms	5	5	100.00
V1	csr_rw	adc_ctrl_csr_rw	3.570s	557.208us	20	20	100.00
V1	csr_bit_bash	adc_ctrl_csr_bit_bash	1.576m	52.969ms	5	5	100.00
V1	csr_aliasing	adc_ctrl_csr_aliasing	9.540s	1.100ms	5	5	100.00
V1	csr_mem_rw_with_rand_reset	adc_ctrl_csr_mem_rw_with_rand_reset	3.390s	497.353us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	adc_ctrl_csr_rw	3.570s	557.208us	20	20	100.00
		adc_ctrl_csr_aliasing	9.540s	1.100ms	5	5	100.00
V1		TOTAL			105	105	100.00
V2	filters_polled	adc_ctrl_filters_polled	25.741m	483.700ms	50	50	100.00
V2	filters_polled_fixed	adc_ctrl_filters_polled_fixed	23.221m	484.845ms	50	50	100.00
V2	filters_interrupt	adc_ctrl_filters_interrupt	26.186m	492.189ms	50	50	100.00
V2	filters_interrupt_fixed	adc_ctrl_filters_interrupt_fixed	22.158m	487.312ms	50	50	100.00
V2	filters_wakeup	adc_ctrl_filters_wakeup	33.471m	634.846ms	50	50	100.00
V2	filters_wakeup_fixed	adc_ctrl_filters_wakeup_fixed	31.513m	603.645ms	50	50	100.00
V2	filters_both	adc_ctrl_filters_both	26.170m	540.131ms	49	50	98.00
V2	clock_gating	adc_ctrl_clock_gating	22.861m	604.583ms	50	50	100.00
V2	poweron_counter	adc_ctrl_poweron_counter	21.730s	5.419ms	50	50	100.00
V2	lowpower_counter	adc_ctrl_lowpower_counter	2.421m	36.115ms	50	50	100.00
V2	fsm_reset	adc_ctrl_fsm_reset	17.861m	129.116ms	50	50	100.00
V2	stress_all	adc_ctrl_stress_all	35.741m	1.258s	50	50	100.00
V2	alert_test	adc_ctrl_alert_test	2.900s	459.270us	50	50	100.00
V2	intr_test	adc_ctrl_intr_test	3.200s	510.792us	50	50	100.00
V2	tl_d_oob_addr_access	adc_ctrl_tl_errors	5.970s	671.464us	20	20	100.00
V2	tl_d_illegal_access	adc_ctrl_tl_errors	5.970s	671.464us	20	20	100.00
V2	tl_d_outstanding_access	adc_ctrl_csr_hw_reset	5.900s	1.059ms	5	5	100.00
		adc_ctrl_csr_rw	3.570s	557.208us	20	20	100.00
		adc_ctrl_csr_aliasing	9.540s	1.100ms	5	5	100.00
		adc_ctrl_same_csr_outstanding	22.290s	4.403ms	20	20	100.00
V2	tl_d_partial_access	adc_ctrl_csr_hw_reset	5.900s	1.059ms	5	5	100.00
		adc_ctrl_csr_rw	3.570s	557.208us	20	20	100.00
		adc_ctrl_csr_aliasing	9.540s	1.100ms	5	5	100.00
		adc_ctrl_same_csr_outstanding	22.290s	4.403ms	20	20	100.00
V2		TOTAL			739	740	99.86
V2S	tl_intg_err	adc_ctrl_sec_cm	17.730s	4.298ms	5	5	100.00
		adc_ctrl_tl_intg_err	36.240s	8.367ms	20	20	100.00
V2S	sec_cm_bus_integrity	adc_ctrl_tl_intg_err	36.240s	8.367ms	20	20	100.00
V2S		TOTAL			25	25	100.00
V3	stress_all_with_rand_reset	adc_ctrl_stress_all_with_rand_reset	1.380m	224.156ms	49	50	98.00
V3		TOTAL			49	50	98.00
		TOTAL			918	920	99.78

Testplan Progress

Items	Total	Written	Passing	Progress
V1	6	6	6	100.00
V2	16	16	15	93.75
V2S	2	2	2	100.00
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
97.62	99.07	96.67	100.00	100.00	98.83	98.33	90.47

Failure Buckets

• Offending '(np_sample_cnt_q == '0)' has 1 failures:

  • Test adc_ctrl_stress_all_with_rand_reset has 1 failures.

    • 12.adc_ctrl_stress_all_with_rand_reset.26360049549133894195241127161949928153919845205246848798655243651347292559470
      Line 248, in log /workspaces/repo/scratch/os_regression_2024_09_03/adc_ctrl-sim-vcs/12.adc_ctrl_stress_all_with_rand_reset/latest/run.log

            Offending '(np_sample_cnt_q == '0)'
        UVM_ERROR @ 4128180668 ps: (adc_ctrl_fsm.sv:384) [ASSERT FAILED] NpCntClrPwrDn_A
        UVM_INFO @ 4128180668 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_FATAL (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue has 1 failures:

  • Test adc_ctrl_filters_both has 1 failures.

    • 23.adc_ctrl_filters_both.59910908858076435116134091589215074321817937873997222597548292193037888785031
      Line 170, in log /workspaces/repo/scratch/os_regression_2024_09_03/adc_ctrl-sim-vcs/23.adc_ctrl_filters_both/latest/run.log

        UVM_FATAL @ 600000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 600000000000 ps hit, indicating a probable testbench issue
        UVM_INFO @ 600000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

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