ADC_CTRL Simulation Results

Monday September 09 2024 02:20:26 UTC

GitHub Revision: af2d1709f9

Branch: os_regression_2024_09_08

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 13980492992314588037778262839223440914483141513139750793389284041724730149540

Test Results

Stage Name Tests Max Job Runtime Simulated Time Passing Total Pass Rate
V1 smoke adc_ctrl_smoke 29.800s 5.583ms 50 50 100.00
V1 csr_hw_reset adc_ctrl_csr_hw_reset 7.530s 1.266ms 5 5 100.00
V1 csr_rw adc_ctrl_csr_rw 4.100s 550.789us 20 20 100.00
V1 csr_bit_bash adc_ctrl_csr_bit_bash 1.075m 46.004ms 5 5 100.00
V1 csr_aliasing adc_ctrl_csr_aliasing 9.190s 1.221ms 5 5 100.00
V1 csr_mem_rw_with_rand_reset adc_ctrl_csr_mem_rw_with_rand_reset 4.040s 511.776us 20 20 100.00
V1 regwen_csr_and_corresponding_lockable_csr adc_ctrl_csr_rw 4.100s 550.789us 20 20 100.00
adc_ctrl_csr_aliasing 9.190s 1.221ms 5 5 100.00
V1 TOTAL 105 105 100.00
V2 filters_polled adc_ctrl_filters_polled 27.538m 501.500ms 50 50 100.00
V2 filters_polled_fixed adc_ctrl_filters_polled_fixed 28.048m 499.891ms 50 50 100.00
V2 filters_interrupt adc_ctrl_filters_interrupt 28.620m 495.581ms 50 50 100.00
V2 filters_interrupt_fixed adc_ctrl_filters_interrupt_fixed 27.014m 497.520ms 50 50 100.00
V2 filters_wakeup adc_ctrl_filters_wakeup 27.070m 558.421ms 50 50 100.00
V2 filters_wakeup_fixed adc_ctrl_filters_wakeup_fixed 28.839m 608.641ms 50 50 100.00
V2 filters_both adc_ctrl_filters_both 25.796m 513.625ms 50 50 100.00
V2 clock_gating adc_ctrl_clock_gating 27.380m 484.789ms 50 50 100.00
V2 poweron_counter adc_ctrl_poweron_counter 23.250s 4.069ms 50 50 100.00
V2 lowpower_counter adc_ctrl_lowpower_counter 3.267m 42.153ms 50 50 100.00
V2 fsm_reset adc_ctrl_fsm_reset 16.890m 137.797ms 50 50 100.00
V2 stress_all adc_ctrl_stress_all 47.271m 718.489ms 50 50 100.00
V2 alert_test adc_ctrl_alert_test 3.080s 405.121us 50 50 100.00
V2 intr_test adc_ctrl_intr_test 3.660s 514.849us 50 50 100.00
V2 tl_d_oob_addr_access adc_ctrl_tl_errors 5.910s 578.871us 20 20 100.00
V2 tl_d_illegal_access adc_ctrl_tl_errors 5.910s 578.871us 20 20 100.00
V2 tl_d_outstanding_access adc_ctrl_csr_hw_reset 7.530s 1.266ms 5 5 100.00
adc_ctrl_csr_rw 4.100s 550.789us 20 20 100.00
adc_ctrl_csr_aliasing 9.190s 1.221ms 5 5 100.00
adc_ctrl_same_csr_outstanding 31.900s 5.056ms 20 20 100.00
V2 tl_d_partial_access adc_ctrl_csr_hw_reset 7.530s 1.266ms 5 5 100.00
adc_ctrl_csr_rw 4.100s 550.789us 20 20 100.00
adc_ctrl_csr_aliasing 9.190s 1.221ms 5 5 100.00
adc_ctrl_same_csr_outstanding 31.900s 5.056ms 20 20 100.00
V2 TOTAL 740 740 100.00
V2S tl_intg_err adc_ctrl_sec_cm 24.610s 4.655ms 5 5 100.00
adc_ctrl_tl_intg_err 37.490s 7.992ms 20 20 100.00
V2S sec_cm_bus_integrity adc_ctrl_tl_intg_err 37.490s 7.992ms 20 20 100.00
V2S TOTAL 25 25 100.00
V3 stress_all_with_rand_reset adc_ctrl_stress_all_with_rand_reset 1.619m 170.459ms 50 50 100.00
V3 TOTAL 50 50 100.00
TOTAL 920 920 100.00

Testplan Progress

Items Total Written Passing Progress
V1 6 6 6 100.00
V2 16 16 16 100.00
V2S 2 2 2 100.00
V3 1 1 1 100.00

Coverage Results

Coverage Dashboard

SCORE LINE COND TOGGLE FSM BRANCH ASSERT GROUP
97.72 99.07 96.67 100.00 100.00 98.83 98.33 91.14

Past Results