ADC_CTRL Simulation Results

Tuesday September 10 2024 22:04:06 UTC

GitHub Revision: 25b1acbf68

Branch: os_regression_2024_09_10

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 115096073277204595231937901342804627564470767004707790242822318429579153097636

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	adc_ctrl_smoke	27.960s	5.994ms	50	50	100.00
V1	csr_hw_reset	adc_ctrl_csr_hw_reset	4.960s	796.090us	5	5	100.00
V1	csr_rw	adc_ctrl_csr_rw	3.090s	428.159us	20	20	100.00
V1	csr_bit_bash	adc_ctrl_csr_bit_bash	2.018m	26.926ms	5	5	100.00
V1	csr_aliasing	adc_ctrl_csr_aliasing	6.820s	1.193ms	5	5	100.00
V1	csr_mem_rw_with_rand_reset	adc_ctrl_csr_mem_rw_with_rand_reset	3.760s	555.087us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	adc_ctrl_csr_rw	3.090s	428.159us	20	20	100.00
		adc_ctrl_csr_aliasing	6.820s	1.193ms	5	5	100.00
V1		TOTAL			105	105	100.00
V2	filters_polled	adc_ctrl_filters_polled	29.326m	494.030ms	50	50	100.00
V2	filters_polled_fixed	adc_ctrl_filters_polled_fixed	28.518m	493.587ms	50	50	100.00
V2	filters_interrupt	adc_ctrl_filters_interrupt	24.103m	490.739ms	50	50	100.00
V2	filters_interrupt_fixed	adc_ctrl_filters_interrupt_fixed	23.051m	492.201ms	50	50	100.00
V2	filters_wakeup	adc_ctrl_filters_wakeup	23.875m	546.955ms	50	50	100.00
V2	filters_wakeup_fixed	adc_ctrl_filters_wakeup_fixed	31.167m	595.968ms	50	50	100.00
V2	filters_both	adc_ctrl_filters_both	31.069m	600.000ms	49	50	98.00
V2	clock_gating	adc_ctrl_clock_gating	23.091m	604.665ms	50	50	100.00
V2	poweron_counter	adc_ctrl_poweron_counter	21.660s	5.139ms	50	50	100.00
V2	lowpower_counter	adc_ctrl_lowpower_counter	2.573m	45.410ms	50	50	100.00
V2	fsm_reset	adc_ctrl_fsm_reset	17.004m	122.187ms	50	50	100.00
V2	stress_all	adc_ctrl_stress_all	1.091h	1.401s	50	50	100.00
V2	alert_test	adc_ctrl_alert_test	3.040s	496.733us	50	50	100.00
V2	intr_test	adc_ctrl_intr_test	3.090s	495.250us	50	50	100.00
V2	tl_d_oob_addr_access	adc_ctrl_tl_errors	5.270s	414.024us	20	20	100.00
V2	tl_d_illegal_access	adc_ctrl_tl_errors	5.270s	414.024us	20	20	100.00
V2	tl_d_outstanding_access	adc_ctrl_csr_hw_reset	4.960s	796.090us	5	5	100.00
		adc_ctrl_csr_rw	3.090s	428.159us	20	20	100.00
		adc_ctrl_csr_aliasing	6.820s	1.193ms	5	5	100.00
		adc_ctrl_same_csr_outstanding	24.500s	5.636ms	20	20	100.00
V2	tl_d_partial_access	adc_ctrl_csr_hw_reset	4.960s	796.090us	5	5	100.00
		adc_ctrl_csr_rw	3.090s	428.159us	20	20	100.00
		adc_ctrl_csr_aliasing	6.820s	1.193ms	5	5	100.00
		adc_ctrl_same_csr_outstanding	24.500s	5.636ms	20	20	100.00
V2		TOTAL			739	740	99.86
V2S	tl_intg_err	adc_ctrl_sec_cm	18.220s	3.953ms	5	5	100.00
		adc_ctrl_tl_intg_err	23.130s	4.424ms	20	20	100.00
V2S	sec_cm_bus_integrity	adc_ctrl_tl_intg_err	23.130s	4.424ms	20	20	100.00
V2S		TOTAL			25	25	100.00
V3	stress_all_with_rand_reset	adc_ctrl_stress_all_with_rand_reset	1.394m	162.792ms	50	50	100.00
V3		TOTAL			50	50	100.00
		TOTAL			919	920	99.89

Testplan Progress

Items	Total	Written	Passing	Progress
V1	6	6	6	100.00
V2	16	16	15	93.75
V2S	2	2	2	100.00
V3	1	1	1	100.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
97.77	99.07	96.67	100.00	100.00	98.83	98.33	91.49

Failure Buckets

• UVM_FATAL (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue has 1 failures:
  • Test adc_ctrl_filters_both has 1 failures.

    • 3.adc_ctrl_filters_both.29329770566661245800958822029736139218958818838739089371901689833928761272796
      Line 170, in log /workspaces/repo/scratch/os_regression_2024_09_10/adc_ctrl-sim-vcs/3.adc_ctrl_filters_both/latest/run.log

        UVM_FATAL @ 600000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 600000000000 ps hit, indicating a probable testbench issue
        UVM_INFO @ 600000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

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