AES/MASKED Simulation Results

Thursday February 29 2024 20:02:24 UTC

GitHub Revision: `e0c4026501`

Branch: os_regression

Simulator: XCELIUM

Build randomization enabled with --build-seed 37435771356197831901593787335841447308974032110687249165442170486932885997295

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	wake_up	aes_wake_up	4.000s	113.979us	1	1	100.00
V1	smoke	aes_smoke	17.000s	439.752us	50	50	100.00
V1	csr_hw_reset	aes_csr_hw_reset	4.000s	215.865us	5	5	100.00
V1	csr_rw	aes_csr_rw	4.000s	59.747us	20	20	100.00
V1	csr_bit_bash	aes_csr_bit_bash	11.000s	716.898us	5	5	100.00
V1	csr_aliasing	aes_csr_aliasing	6.000s	99.208us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	aes_csr_mem_rw_with_rand_reset	4.000s	82.964us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	aes_csr_rw	4.000s	59.747us	20	20	100.00
		aes_csr_aliasing	6.000s	99.208us	5	5	100.00
V1		TOTAL			106	106	100.00
V2	algorithm	aes_smoke	17.000s	439.752us	50	50	100.00
		aes_config_error	11.000s	291.817us	50	50	100.00
		aes_stress	15.000s	465.851us	50	50	100.00
V2	key_length	aes_smoke	17.000s	439.752us	50	50	100.00
		aes_config_error	11.000s	291.817us	50	50	100.00
		aes_stress	15.000s	465.851us	50	50	100.00
V2	back2back	aes_stress	15.000s	465.851us	50	50	100.00
		aes_b2b	37.000s	1.310ms	50	50	100.00
V2	backpressure	aes_stress	15.000s	465.851us	50	50	100.00
V2	multi_message	aes_smoke	17.000s	439.752us	50	50	100.00
		aes_config_error	11.000s	291.817us	50	50	100.00
		aes_stress	15.000s	465.851us	50	50	100.00
		aes_alert_reset	1.533m	3.430ms	50	50	100.00
V2	failure_test	aes_man_cfg_err	13.000s	105.522us	50	50	100.00
		aes_config_error	11.000s	291.817us	50	50	100.00
		aes_alert_reset	1.533m	3.430ms	50	50	100.00
V2	trigger_clear_test	aes_clear	5.133m	8.076ms	50	50	100.00
V2	nist_test_vectors	aes_nist_vectors	13.000s	195.259us	1	1	100.00
V2	reset_recovery	aes_alert_reset	1.533m	3.430ms	50	50	100.00
V2	stress	aes_stress	15.000s	465.851us	50	50	100.00
V2	sideload	aes_stress	15.000s	465.851us	50	50	100.00
		aes_sideload	15.000s	2.502ms	50	50	100.00
V2	deinitialization	aes_deinit	16.000s	533.975us	50	50	100.00
V2	stress_all	aes_stress_all	1.150m	793.406us	10	10	100.00
V2	alert_test	aes_alert_test	13.000s	84.206us	50	50	100.00
V2	tl_d_oob_addr_access	aes_tl_errors	6.000s	207.426us	20	20	100.00
V2	tl_d_illegal_access	aes_tl_errors	6.000s	207.426us	20	20	100.00
V2	tl_d_outstanding_access	aes_csr_hw_reset	4.000s	215.865us	5	5	100.00
		aes_csr_rw	4.000s	59.747us	20	20	100.00
		aes_csr_aliasing	6.000s	99.208us	5	5	100.00
		aes_same_csr_outstanding	5.000s	82.518us	20	20	100.00
V2	tl_d_partial_access	aes_csr_hw_reset	4.000s	215.865us	5	5	100.00
		aes_csr_rw	4.000s	59.747us	20	20	100.00
		aes_csr_aliasing	6.000s	99.208us	5	5	100.00
		aes_same_csr_outstanding	5.000s	82.518us	20	20	100.00
V2		TOTAL			501	501	100.00
V2S	reseeding	aes_reseed	49.000s	1.452ms	49	50	98.00
V2S	fault_inject	aes_fi	38.000s	1.293ms	50	50	100.00
		aes_control_fi	51.000s	10.010ms	275	300	91.67
		aes_cipher_fi	51.000s	10.004ms	338	350	96.57
V2S	shadow_reg_update_error	aes_shadow_reg_errors	4.000s	178.854us	20	20	100.00
V2S	shadow_reg_read_clear_staged_value	aes_shadow_reg_errors	4.000s	178.854us	20	20	100.00
V2S	shadow_reg_storage_error	aes_shadow_reg_errors	4.000s	178.854us	20	20	100.00
V2S	shadowed_reset_glitch	aes_shadow_reg_errors	4.000s	178.854us	20	20	100.00
V2S	shadow_reg_update_error_with_csr_rw	aes_shadow_reg_errors_with_csr_rw	5.000s	105.450us	20	20	100.00
V2S	tl_intg_err	aes_sec_cm	11.000s	946.071us	5	5	100.00
		aes_tl_intg_err	7.000s	1.510ms	20	20	100.00
V2S	sec_cm_bus_integrity	aes_tl_intg_err	7.000s	1.510ms	20	20	100.00
V2S	sec_cm_lc_escalate_en_intersig_mubi	aes_alert_reset	1.533m	3.430ms	50	50	100.00
V2S	sec_cm_main_config_shadow	aes_shadow_reg_errors	4.000s	178.854us	20	20	100.00
V2S	sec_cm_main_config_sparse	aes_smoke	17.000s	439.752us	50	50	100.00
		aes_stress	15.000s	465.851us	50	50	100.00
		aes_alert_reset	1.533m	3.430ms	50	50	100.00
		aes_core_fi	1.567m	10.002ms	67	70	95.71
V2S	sec_cm_aux_config_shadow	aes_shadow_reg_errors	4.000s	178.854us	20	20	100.00
V2S	sec_cm_aux_config_regwen	aes_readability	9.000s	52.437us	50	50	100.00
		aes_stress	15.000s	465.851us	50	50	100.00
V2S	sec_cm_key_sideload	aes_stress	15.000s	465.851us	50	50	100.00
		aes_sideload	15.000s	2.502ms	50	50	100.00
V2S	sec_cm_key_sw_unreadable	aes_readability	9.000s	52.437us	50	50	100.00
V2S	sec_cm_data_reg_sw_unreadable	aes_readability	9.000s	52.437us	50	50	100.00
V2S	sec_cm_key_sec_wipe	aes_readability	9.000s	52.437us	50	50	100.00
V2S	sec_cm_iv_config_sec_wipe	aes_readability	9.000s	52.437us	50	50	100.00
V2S	sec_cm_data_reg_sec_wipe	aes_readability	9.000s	52.437us	50	50	100.00
V2S	sec_cm_data_reg_key_sca	aes_stress	15.000s	465.851us	50	50	100.00
V2S	sec_cm_key_masking	aes_stress	15.000s	465.851us	50	50	100.00
V2S	sec_cm_main_fsm_sparse	aes_fi	38.000s	1.293ms	50	50	100.00
V2S	sec_cm_main_fsm_redun	aes_fi	38.000s	1.293ms	50	50	100.00
		aes_control_fi	51.000s	10.010ms	275	300	91.67
		aes_cipher_fi	51.000s	10.004ms	338	350	96.57
		aes_ctr_fi	9.000s	156.614us	50	50	100.00
V2S	sec_cm_cipher_fsm_sparse	aes_fi	38.000s	1.293ms	50	50	100.00
V2S	sec_cm_cipher_fsm_redun	aes_fi	38.000s	1.293ms	50	50	100.00
		aes_control_fi	51.000s	10.010ms	275	300	91.67
		aes_cipher_fi	51.000s	10.004ms	338	350	96.57
V2S	sec_cm_cipher_ctr_redun	aes_cipher_fi	51.000s	10.004ms	338	350	96.57
V2S	sec_cm_ctr_fsm_sparse	aes_fi	38.000s	1.293ms	50	50	100.00
V2S	sec_cm_ctr_fsm_redun	aes_fi	38.000s	1.293ms	50	50	100.00
		aes_control_fi	51.000s	10.010ms	275	300	91.67
		aes_ctr_fi	9.000s	156.614us	50	50	100.00
V2S	sec_cm_ctrl_sparse	aes_fi	38.000s	1.293ms	50	50	100.00
		aes_control_fi	51.000s	10.010ms	275	300	91.67
		aes_cipher_fi	51.000s	10.004ms	338	350	96.57
		aes_ctr_fi	9.000s	156.614us	50	50	100.00
V2S	sec_cm_main_fsm_global_esc	aes_alert_reset	1.533m	3.430ms	50	50	100.00
V2S	sec_cm_main_fsm_local_esc	aes_fi	38.000s	1.293ms	50	50	100.00
		aes_control_fi	51.000s	10.010ms	275	300	91.67
		aes_cipher_fi	51.000s	10.004ms	338	350	96.57
		aes_ctr_fi	9.000s	156.614us	50	50	100.00
V2S	sec_cm_cipher_fsm_local_esc	aes_fi	38.000s	1.293ms	50	50	100.00
		aes_control_fi	51.000s	10.010ms	275	300	91.67
		aes_cipher_fi	51.000s	10.004ms	338	350	96.57
		aes_ctr_fi	9.000s	156.614us	50	50	100.00
V2S	sec_cm_ctr_fsm_local_esc	aes_fi	38.000s	1.293ms	50	50	100.00
		aes_control_fi	51.000s	10.010ms	275	300	91.67
		aes_ctr_fi	9.000s	156.614us	50	50	100.00
V2S	sec_cm_data_reg_local_esc	aes_fi	38.000s	1.293ms	50	50	100.00
		aes_control_fi	51.000s	10.010ms	275	300	91.67
		aes_cipher_fi	51.000s	10.004ms	338	350	96.57
V2S		TOTAL			944	985	95.84
V3	stress_all_with_rand_reset	aes_stress_all_with_rand_reset	2.417m	18.434ms	0	10	0.00
V3		TOTAL			0	10	0.00
		TOTAL			1551	1602	96.82

Testplan Progress

Items	Total	Written	Passing	Progress
V1	7	7	7	100.00
V2	13	13	13	100.00
V2S	11	11	7	63.64
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

Score	Block	Branch	Statement	Expression	Toggle	Fsm	Assertion	CoverGroup
98.58	98.95	97.36	99.45	95.80	97.72	100.00	99.11	97.01

Failure Buckets

Job aes_masked-sim-xcelium_run_default killed due to: Exit reason: User job exceeded runlimit: User job timed out has 17 failures:
- Test aes_control_fi has 15 failures.
  - 10.aes_control_fi.76048566465394877542420753566161550060084206449998990996758286965095449342377
    Log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/10.aes_control_fi/latest/run.log
```
  Job ID: smart:b6ff95c3-a092-4b21-97e2-5eed6d375624
```
  - 40.aes_control_fi.47956680232245762041549766832085639365530113489662261534319182281774424627085
    Log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/40.aes_control_fi/latest/run.log
```
  Job ID: smart:fd7ca724-d4a4-4d07-b66b-4e5865da9fae
```
  - ... and 13 more failures.
- Test aes_cipher_fi has 2 failures.
  - 14.aes_cipher_fi.83109923046730421635377450740599270445349330290728266763051033973367452664352
    Log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/14.aes_cipher_fi/latest/run.log
```
  Job ID: smart:7d82db90-440c-4654-b6ee-cf37229a4e5d
```
  - 157.aes_cipher_fi.71486976356015529556805499726161730986129231979529957481039118797979871872259
    Log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/157.aes_cipher_fi/latest/run.log
```
  Job ID: smart:d490c7a5-7c22-4f5b-838f-66f1f474cf7f
```
UVM_FATAL (aes_control_fi_vseq.sv:62) [aes_control_fi_vseq] wait timeout occurred! has 10 failures:
- Test aes_control_fi has 10 failures.
  - 13.aes_control_fi.8807875925060635445456299592424822693057413594209631958522849904803956664092
    Line 328, in log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/13.aes_control_fi/latest/run.log
```
  UVM_FATAL @ 10040375271 ps: (aes_control_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_control_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10040375271 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 36.aes_control_fi.9528928390238547774087009303930957947303873450097428496947827462466655767876
    Line 328, in log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/36.aes_control_fi/latest/run.log
```
  UVM_FATAL @ 10009661576 ps: (aes_control_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_control_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10009661576 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 8 more failures.
UVM_FATAL (aes_cipher_fi_vseq.sv:62) [aes_cipher_fi_vseq] wait timeout occurred! has 10 failures:
- Test aes_cipher_fi has 10 failures.
  - 17.aes_cipher_fi.68682832786112033641546290927341886097798250967615884100665556096436713588951
    Line 320, in log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/17.aes_cipher_fi/latest/run.log
```
  UVM_FATAL @ 10008739318 ps: (aes_cipher_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_cipher_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10008739318 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 113.aes_cipher_fi.71750153537864733040770782376555523136531688613780404107842634726263368604322
    Line 318, in log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/113.aes_cipher_fi/latest/run.log
```
  UVM_FATAL @ 10017552153 ps: (aes_cipher_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_cipher_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10017552153 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 8 more failures.

UVM_ERROR (uvm_sequencer_base.svh:757) sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'sequencer' for sequence 'sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues has 6 failures:

Test aes_stress_all_with_rand_reset has 6 failures.

2.aes_stress_all_with_rand_reset.72777670439711208527359753008446598500205932995857968628561270017604780919912
Line 1321, in log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/2.aes_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 5626033784 ps: (uvm_sequencer_base.svh:757) uvm_test_top.env.keymgr_sideload_agent.sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'uvm_test_top.env.keymgr_sideload_agent.sequencer' for sequence 'uvm_test_top.env.virtual_sequencer.aes_reseed_vseq.sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues
  UVM_INFO @ 5626033784 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

3.aes_stress_all_with_rand_reset.32808111512081922449780263929345312695938345067722198442027896599479377017473
Line 560, in log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/3.aes_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 750891256 ps: (uvm_sequencer_base.svh:757) uvm_test_top.env.keymgr_sideload_agent.sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'uvm_test_top.env.keymgr_sideload_agent.sequencer' for sequence 'uvm_test_top.env.virtual_sequencer.aes_reseed_vseq.sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues
  UVM_INFO @ 750891256 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 4 more failures.

Exit reason: Error: User command failed UVM_ERROR (uvm_sequencer_base.svh:757) sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'sequencer' for sequence 'sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues has 4 failures:

Test aes_stress_all_with_rand_reset has 4 failures.

0.aes_stress_all_with_rand_reset.114164157115453360137229762582945610145776855165876937849826058596409669894212
Line 773, in log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/0.aes_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 635689415 ps: (uvm_sequencer_base.svh:757) uvm_test_top.env.keymgr_sideload_agent.sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'uvm_test_top.env.keymgr_sideload_agent.sequencer' for sequence 'uvm_test_top.env.virtual_sequencer.aes_reseed_vseq.sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues
  UVM_INFO @ 635689415 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

1.aes_stress_all_with_rand_reset.55119526888307820864884574262582974700285244592546487662699831287605949497428
Line 1063, in log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/1.aes_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 5555564510 ps: (uvm_sequencer_base.svh:757) uvm_test_top.env.keymgr_sideload_agent.sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'uvm_test_top.env.keymgr_sideload_agent.sequencer' for sequence 'uvm_test_top.env.virtual_sequencer.aes_stress_vseq.sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues
  UVM_INFO @ 5555564510 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 2 more failures.

UVM_FATAL (aes_core_fi_vseq.sv:66) [aes_core_fi_vseq] wait timeout occurred! has 3 failures:
- Test aes_core_fi has 3 failures.
  - 6.aes_core_fi.95793431530470304895023843676268162531825558415550799103638780563443885610945
    Line 315, in log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/6.aes_core_fi/latest/run.log
```
  UVM_FATAL @ 10006228739 ps: (aes_core_fi_vseq.sv:66) [uvm_test_top.env.virtual_sequencer.aes_core_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10006228739 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 14.aes_core_fi.46463888069662906573217014337480862145193644062977757360296498679111454805522
    Line 326, in log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/14.aes_core_fi/latest/run.log
```
  UVM_FATAL @ 10002203544 ps: (aes_core_fi_vseq.sv:66) [uvm_test_top.env.virtual_sequencer.aes_core_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10002203544 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 1 more failures.
Exit reason: Error: User command failed UVM_FATAL (aes_reseed_vseq.sv:40) [aes_reseed_vseq] Check failed request_seen | finished_all_msgs == *'b* (* [*] vs * [*]) has 1 failures:
- Test aes_reseed has 1 failures.
  - 38.aes_reseed.21097241615526330149671657185526452275874793213290064244425271722032170243712
    Line 1919, in log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/38.aes_reseed/latest/run.log
```
  UVM_FATAL @ 102920355 ps: (aes_reseed_vseq.sv:40) [uvm_test_top.env.virtual_sequencer.aes_reseed_vseq] Check failed request_seen | finished_all_msgs == 1'b1 (0 [0x0] vs 1 [0x1])
  UVM_INFO @ 102920355 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```