AES/MASKED Simulation Results

Sunday March 17 2024 19:02:52 UTC

GitHub Revision: `c187a82ee8`

Branch: os_regression

Simulator: XCELIUM

Build randomization enabled with --build-seed 28440605375541353837496064678278045899395893237469128852560697715229879921060

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	wake_up	aes_wake_up	4.000s	106.738us	1	1	100.00
V1	smoke	aes_smoke	13.000s	123.162us	50	50	100.00
V1	csr_hw_reset	aes_csr_hw_reset	8.000s	60.685us	5	5	100.00
V1	csr_rw	aes_csr_rw	13.000s	64.452us	20	20	100.00
V1	csr_bit_bash	aes_csr_bit_bash	7.000s	341.227us	5	5	100.00
V1	csr_aliasing	aes_csr_aliasing	5.000s	68.521us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	aes_csr_mem_rw_with_rand_reset	13.000s	97.832us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	aes_csr_rw	13.000s	64.452us	20	20	100.00
		aes_csr_aliasing	5.000s	68.521us	5	5	100.00
V1		TOTAL			106	106	100.00
V2	algorithm	aes_smoke	13.000s	123.162us	50	50	100.00
		aes_config_error	32.000s	997.122us	50	50	100.00
		aes_stress	29.000s	781.602us	50	50	100.00
V2	key_length	aes_smoke	13.000s	123.162us	50	50	100.00
		aes_config_error	32.000s	997.122us	50	50	100.00
		aes_stress	29.000s	781.602us	50	50	100.00
V2	back2back	aes_stress	29.000s	781.602us	50	50	100.00
		aes_b2b	1.767m	1.445ms	50	50	100.00
V2	backpressure	aes_stress	29.000s	781.602us	50	50	100.00
V2	multi_message	aes_smoke	13.000s	123.162us	50	50	100.00
		aes_config_error	32.000s	997.122us	50	50	100.00
		aes_stress	29.000s	781.602us	50	50	100.00
		aes_alert_reset	37.000s	1.341ms	50	50	100.00
V2	failure_test	aes_man_cfg_err	14.000s	139.317us	50	50	100.00
		aes_config_error	32.000s	997.122us	50	50	100.00
		aes_alert_reset	37.000s	1.341ms	50	50	100.00
V2	trigger_clear_test	aes_clear	19.000s	531.780us	50	50	100.00
V2	nist_test_vectors	aes_nist_vectors	37.000s	3.315ms	1	1	100.00
V2	reset_recovery	aes_alert_reset	37.000s	1.341ms	50	50	100.00
V2	stress	aes_stress	29.000s	781.602us	50	50	100.00
V2	sideload	aes_stress	29.000s	781.602us	50	50	100.00
		aes_sideload	36.000s	765.764us	50	50	100.00
V2	deinitialization	aes_deinit	12.000s	127.049us	50	50	100.00
V2	stress_all	aes_stress_all	1.300m	12.380ms	10	10	100.00
V2	alert_test	aes_alert_test	13.000s	76.648us	50	50	100.00
V2	tl_d_oob_addr_access	aes_tl_errors	20.000s	192.615us	20	20	100.00
V2	tl_d_illegal_access	aes_tl_errors	20.000s	192.615us	20	20	100.00
V2	tl_d_outstanding_access	aes_csr_hw_reset	8.000s	60.685us	5	5	100.00
		aes_csr_rw	13.000s	64.452us	20	20	100.00
		aes_csr_aliasing	5.000s	68.521us	5	5	100.00
		aes_same_csr_outstanding	9.000s	228.859us	20	20	100.00
V2	tl_d_partial_access	aes_csr_hw_reset	8.000s	60.685us	5	5	100.00
		aes_csr_rw	13.000s	64.452us	20	20	100.00
		aes_csr_aliasing	5.000s	68.521us	5	5	100.00
		aes_same_csr_outstanding	9.000s	228.859us	20	20	100.00
V2		TOTAL			501	501	100.00
V2S	reseeding	aes_reseed	4.600m	7.804ms	50	50	100.00
V2S	fault_inject	aes_fi	17.000s	218.994us	50	50	100.00
		aes_control_fi	50.000s	10.004ms	285	300	95.00
		aes_cipher_fi	49.000s	10.071ms	340	350	97.14
V2S	shadow_reg_update_error	aes_shadow_reg_errors	8.000s	106.744us	20	20	100.00
V2S	shadow_reg_read_clear_staged_value	aes_shadow_reg_errors	8.000s	106.744us	20	20	100.00
V2S	shadow_reg_storage_error	aes_shadow_reg_errors	8.000s	106.744us	20	20	100.00
V2S	shadowed_reset_glitch	aes_shadow_reg_errors	8.000s	106.744us	20	20	100.00
V2S	shadow_reg_update_error_with_csr_rw	aes_shadow_reg_errors_with_csr_rw	14.000s	161.921us	20	20	100.00
V2S	tl_intg_err	aes_sec_cm	8.000s	529.919us	5	5	100.00
		aes_tl_intg_err	16.000s	489.268us	20	20	100.00
V2S	sec_cm_bus_integrity	aes_tl_intg_err	16.000s	489.268us	20	20	100.00
V2S	sec_cm_lc_escalate_en_intersig_mubi	aes_alert_reset	37.000s	1.341ms	50	50	100.00
V2S	sec_cm_main_config_shadow	aes_shadow_reg_errors	8.000s	106.744us	20	20	100.00
V2S	sec_cm_main_config_sparse	aes_smoke	13.000s	123.162us	50	50	100.00
		aes_stress	29.000s	781.602us	50	50	100.00
		aes_alert_reset	37.000s	1.341ms	50	50	100.00
		aes_core_fi	1.533m	10.010ms	68	70	97.14
V2S	sec_cm_aux_config_shadow	aes_shadow_reg_errors	8.000s	106.744us	20	20	100.00
V2S	sec_cm_aux_config_regwen	aes_readability	8.000s	58.341us	50	50	100.00
		aes_stress	29.000s	781.602us	50	50	100.00
V2S	sec_cm_key_sideload	aes_stress	29.000s	781.602us	50	50	100.00
		aes_sideload	36.000s	765.764us	50	50	100.00
V2S	sec_cm_key_sw_unreadable	aes_readability	8.000s	58.341us	50	50	100.00
V2S	sec_cm_data_reg_sw_unreadable	aes_readability	8.000s	58.341us	50	50	100.00
V2S	sec_cm_key_sec_wipe	aes_readability	8.000s	58.341us	50	50	100.00
V2S	sec_cm_iv_config_sec_wipe	aes_readability	8.000s	58.341us	50	50	100.00
V2S	sec_cm_data_reg_sec_wipe	aes_readability	8.000s	58.341us	50	50	100.00
V2S	sec_cm_data_reg_key_sca	aes_stress	29.000s	781.602us	50	50	100.00
V2S	sec_cm_key_masking	aes_stress	29.000s	781.602us	50	50	100.00
V2S	sec_cm_main_fsm_sparse	aes_fi	17.000s	218.994us	50	50	100.00
V2S	sec_cm_main_fsm_redun	aes_fi	17.000s	218.994us	50	50	100.00
		aes_control_fi	50.000s	10.004ms	285	300	95.00
		aes_cipher_fi	49.000s	10.071ms	340	350	97.14
		aes_ctr_fi	9.000s	60.373us	50	50	100.00
V2S	sec_cm_cipher_fsm_sparse	aes_fi	17.000s	218.994us	50	50	100.00
V2S	sec_cm_cipher_fsm_redun	aes_fi	17.000s	218.994us	50	50	100.00
		aes_control_fi	50.000s	10.004ms	285	300	95.00
		aes_cipher_fi	49.000s	10.071ms	340	350	97.14
V2S	sec_cm_cipher_ctr_redun	aes_cipher_fi	49.000s	10.071ms	340	350	97.14
V2S	sec_cm_ctr_fsm_sparse	aes_fi	17.000s	218.994us	50	50	100.00
V2S	sec_cm_ctr_fsm_redun	aes_fi	17.000s	218.994us	50	50	100.00
		aes_control_fi	50.000s	10.004ms	285	300	95.00
		aes_ctr_fi	9.000s	60.373us	50	50	100.00
V2S	sec_cm_ctrl_sparse	aes_fi	17.000s	218.994us	50	50	100.00
		aes_control_fi	50.000s	10.004ms	285	300	95.00
		aes_cipher_fi	49.000s	10.071ms	340	350	97.14
		aes_ctr_fi	9.000s	60.373us	50	50	100.00
V2S	sec_cm_main_fsm_global_esc	aes_alert_reset	37.000s	1.341ms	50	50	100.00
V2S	sec_cm_main_fsm_local_esc	aes_fi	17.000s	218.994us	50	50	100.00
		aes_control_fi	50.000s	10.004ms	285	300	95.00
		aes_cipher_fi	49.000s	10.071ms	340	350	97.14
		aes_ctr_fi	9.000s	60.373us	50	50	100.00
V2S	sec_cm_cipher_fsm_local_esc	aes_fi	17.000s	218.994us	50	50	100.00
		aes_control_fi	50.000s	10.004ms	285	300	95.00
		aes_cipher_fi	49.000s	10.071ms	340	350	97.14
		aes_ctr_fi	9.000s	60.373us	50	50	100.00
V2S	sec_cm_ctr_fsm_local_esc	aes_fi	17.000s	218.994us	50	50	100.00
		aes_control_fi	50.000s	10.004ms	285	300	95.00
		aes_ctr_fi	9.000s	60.373us	50	50	100.00
V2S	sec_cm_data_reg_local_esc	aes_fi	17.000s	218.994us	50	50	100.00
		aes_control_fi	50.000s	10.004ms	285	300	95.00
		aes_cipher_fi	49.000s	10.071ms	340	350	97.14
V2S		TOTAL			958	985	97.26
V3	stress_all_with_rand_reset	aes_stress_all_with_rand_reset	3.883m	15.958ms	0	10	0.00
V3		TOTAL			0	10	0.00
		TOTAL			1565	1602	97.69

Testplan Progress

Items	Total	Written	Passing	Progress
V1	7	7	7	100.00
V2	13	13	13	100.00
V2S	11	11	8	72.73
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

Score	Block	Branch	Statement	Expression	Toggle	Fsm	Assertion	CoverGroup
98.54	98.92	97.27	99.42	95.81	97.72	97.78	98.96	96.41

Failure Buckets

Job aes_masked-sim-xcelium_run_default killed due to: Exit reason: User job exceeded runlimit: User job timed out has 15 failures:
- Test aes_control_fi has 11 failures.
  - 3.aes_control_fi.5834545748770258151406978803463341686527596426271380307769302206702200013738
    Log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/3.aes_control_fi/latest/run.log
```
  Job ID: smart:66ceaebe-699f-4fdb-9e26-c1b79511a3c7
```
  - 4.aes_control_fi.88058242360611034756060036549381264785050968492505000846363930541816644993906
    Log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/4.aes_control_fi/latest/run.log
```
  Job ID: smart:f882c3b3-060e-448c-8061-55852824e81f
```
  - ... and 9 more failures.
- Test aes_cipher_fi has 4 failures.
  - 75.aes_cipher_fi.115357505503478193479643881961085631518119314165430429362473365868919136654540
    Log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/75.aes_cipher_fi/latest/run.log
```
  Job ID: smart:09ab83b8-b0ea-4f2d-a9bc-1a37ba855dbb
```
  - 130.aes_cipher_fi.68871917115196503858242789450670585965741661978463119084504482925701470820398
    Log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/130.aes_cipher_fi/latest/run.log
```
  Job ID: smart:ab33293d-7dd0-44f2-aafa-5a93deb508c7
```
  - ... and 2 more failures.

UVM_ERROR (uvm_sequencer_base.svh:757) sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'sequencer' for sequence 'sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues has 9 failures:

Test aes_stress_all_with_rand_reset has 9 failures.

0.aes_stress_all_with_rand_reset.49111489316254079394678557917890223927692940302652690135020338078363210286779
Line 965, in log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/0.aes_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 575722681 ps: (uvm_sequencer_base.svh:757) uvm_test_top.env.keymgr_sideload_agent.sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'uvm_test_top.env.keymgr_sideload_agent.sequencer' for sequence 'uvm_test_top.env.virtual_sequencer.aes_stress_vseq.sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues
  UVM_INFO @ 575722681 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

1.aes_stress_all_with_rand_reset.114201363315722674050341382410797412055427249565323089432255222869776648346721
Line 1113, in log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/1.aes_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 1540777081 ps: (uvm_sequencer_base.svh:757) uvm_test_top.env.keymgr_sideload_agent.sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'uvm_test_top.env.keymgr_sideload_agent.sequencer' for sequence 'uvm_test_top.env.virtual_sequencer.aes_reseed_vseq.sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues
  UVM_INFO @ 1540777081 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 7 more failures.

UVM_FATAL (aes_cipher_fi_vseq.sv:62) [aes_cipher_fi_vseq] wait timeout occurred! has 6 failures:
- Test aes_cipher_fi has 6 failures.
  - 32.aes_cipher_fi.68362021332350206578441931523077508440910935348487322440958510551207922052753
    Line 319, in log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/32.aes_cipher_fi/latest/run.log
```
  UVM_FATAL @ 10026540320 ps: (aes_cipher_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_cipher_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10026540320 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 83.aes_cipher_fi.55669848362265069490082246077237246157482606602799188425017427052806507362884
    Line 316, in log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/83.aes_cipher_fi/latest/run.log
```
  UVM_FATAL @ 10070899578 ps: (aes_cipher_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_cipher_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10070899578 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 4 more failures.
UVM_FATAL (aes_control_fi_vseq.sv:62) [aes_control_fi_vseq] wait timeout occurred! has 4 failures:
- Test aes_control_fi has 4 failures.
  - 118.aes_control_fi.77190426492920394827194354970882374112056543984652546977289039028108786693752
    Line 318, in log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/118.aes_control_fi/latest/run.log
```
  UVM_FATAL @ 10014992488 ps: (aes_control_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_control_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10014992488 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 158.aes_control_fi.111302588792096271682142993676858772412531291199845437950702292223674253630265
    Line 323, in log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/158.aes_control_fi/latest/run.log
```
  UVM_FATAL @ 10004050502 ps: (aes_control_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_control_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10004050502 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 2 more failures.
UVM_FATAL (aes_core_fi_vseq.sv:66) [aes_core_fi_vseq] wait timeout occurred! has 2 failures:
- Test aes_core_fi has 2 failures.
  - 32.aes_core_fi.85197796001476769690628136141989513768108867782289414938954115814676619352181
    Line 321, in log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/32.aes_core_fi/latest/run.log
```
  UVM_FATAL @ 10010369331 ps: (aes_core_fi_vseq.sv:66) [uvm_test_top.env.virtual_sequencer.aes_core_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10010369331 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 42.aes_core_fi.61254778312189975152973770768395710794069307281307745634735349981923853573343
    Line 318, in log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/42.aes_core_fi/latest/run.log
```
  UVM_FATAL @ 10070081586 ps: (aes_core_fi_vseq.sv:66) [uvm_test_top.env.virtual_sequencer.aes_core_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10070081586 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
Exit reason: Error: User command failed UVM_ERROR (uvm_sequencer_base.svh:757) sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'sequencer' for sequence 'sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues has 1 failures:
- Test aes_stress_all_with_rand_reset has 1 failures.
  - 2.aes_stress_all_with_rand_reset.62298485699261952393415166784179876771813230982565796037164386216324760221647
    Line 1029, in log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/2.aes_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 3275814000 ps: (uvm_sequencer_base.svh:757) uvm_test_top.env.keymgr_sideload_agent.sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'uvm_test_top.env.keymgr_sideload_agent.sequencer' for sequence 'uvm_test_top.env.virtual_sequencer.aes_reseed_vseq.sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues
  UVM_INFO @ 3275814000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```