AES/MASKED Simulation Results

Tuesday March 12 2024 19:02:37 UTC

GitHub Revision: `bc285b7382`

Branch: os_regression

Simulator: XCELIUM

Build randomization enabled with --build-seed 8078106501385188224785993882809517173695187907049792415947230968390919037084

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	wake_up	aes_wake_up	5.000s	96.409us	1	1	100.00
V1	smoke	aes_smoke	14.000s	140.673us	50	50	100.00
V1	csr_hw_reset	aes_csr_hw_reset	3.000s	82.369us	5	5	100.00
V1	csr_rw	aes_csr_rw	4.000s	61.114us	20	20	100.00
V1	csr_bit_bash	aes_csr_bit_bash	10.000s	1.912ms	5	5	100.00
V1	csr_aliasing	aes_csr_aliasing	9.000s	129.478us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	aes_csr_mem_rw_with_rand_reset	13.000s	135.812us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	aes_csr_rw	4.000s	61.114us	20	20	100.00
		aes_csr_aliasing	9.000s	129.478us	5	5	100.00
V1		TOTAL			106	106	100.00
V2	algorithm	aes_smoke	14.000s	140.673us	50	50	100.00
		aes_config_error	43.000s	1.503ms	50	50	100.00
		aes_stress	38.000s	2.788ms	50	50	100.00
V2	key_length	aes_smoke	14.000s	140.673us	50	50	100.00
		aes_config_error	43.000s	1.503ms	50	50	100.00
		aes_stress	38.000s	2.788ms	50	50	100.00
V2	back2back	aes_stress	38.000s	2.788ms	50	50	100.00
		aes_b2b	34.000s	796.101us	50	50	100.00
V2	backpressure	aes_stress	38.000s	2.788ms	50	50	100.00
V2	multi_message	aes_smoke	14.000s	140.673us	50	50	100.00
		aes_config_error	43.000s	1.503ms	50	50	100.00
		aes_stress	38.000s	2.788ms	50	50	100.00
		aes_alert_reset	56.000s	3.572ms	50	50	100.00
V2	failure_test	aes_man_cfg_err	11.000s	415.945us	50	50	100.00
		aes_config_error	43.000s	1.503ms	50	50	100.00
		aes_alert_reset	56.000s	3.572ms	50	50	100.00
V2	trigger_clear_test	aes_clear	28.000s	911.944us	50	50	100.00
V2	nist_test_vectors	aes_nist_vectors	18.000s	308.080us	1	1	100.00
V2	reset_recovery	aes_alert_reset	56.000s	3.572ms	50	50	100.00
V2	stress	aes_stress	38.000s	2.788ms	50	50	100.00
V2	sideload	aes_stress	38.000s	2.788ms	50	50	100.00
		aes_sideload	11.000s	1.220ms	50	50	100.00
V2	deinitialization	aes_deinit	10.000s	81.949us	50	50	100.00
V2	stress_all	aes_stress_all	1.417m	1.724ms	10	10	100.00
V2	alert_test	aes_alert_test	8.000s	98.810us	50	50	100.00
V2	tl_d_oob_addr_access	aes_tl_errors	16.000s	505.242us	20	20	100.00
V2	tl_d_illegal_access	aes_tl_errors	16.000s	505.242us	20	20	100.00
V2	tl_d_outstanding_access	aes_csr_hw_reset	3.000s	82.369us	5	5	100.00
		aes_csr_rw	4.000s	61.114us	20	20	100.00
		aes_csr_aliasing	9.000s	129.478us	5	5	100.00
		aes_same_csr_outstanding	9.000s	192.121us	20	20	100.00
V2	tl_d_partial_access	aes_csr_hw_reset	3.000s	82.369us	5	5	100.00
		aes_csr_rw	4.000s	61.114us	20	20	100.00
		aes_csr_aliasing	9.000s	129.478us	5	5	100.00
		aes_same_csr_outstanding	9.000s	192.121us	20	20	100.00
V2		TOTAL			501	501	100.00
V2S	reseeding	aes_reseed	25.000s	857.367us	50	50	100.00
V2S	fault_inject	aes_fi	40.000s	1.920ms	50	50	100.00
		aes_control_fi	48.000s	10.013ms	281	300	93.67
		aes_cipher_fi	47.000s	10.014ms	341	350	97.43
V2S	shadow_reg_update_error	aes_shadow_reg_errors	8.000s	70.343us	20	20	100.00
V2S	shadow_reg_read_clear_staged_value	aes_shadow_reg_errors	8.000s	70.343us	20	20	100.00
V2S	shadow_reg_storage_error	aes_shadow_reg_errors	8.000s	70.343us	20	20	100.00
V2S	shadowed_reset_glitch	aes_shadow_reg_errors	8.000s	70.343us	20	20	100.00
V2S	shadow_reg_update_error_with_csr_rw	aes_shadow_reg_errors_with_csr_rw	8.000s	87.217us	20	20	100.00
V2S	tl_intg_err	aes_sec_cm	11.000s	895.619us	5	5	100.00
		aes_tl_intg_err	14.000s	329.987us	20	20	100.00
V2S	sec_cm_bus_integrity	aes_tl_intg_err	14.000s	329.987us	20	20	100.00
V2S	sec_cm_lc_escalate_en_intersig_mubi	aes_alert_reset	56.000s	3.572ms	50	50	100.00
V2S	sec_cm_main_config_shadow	aes_shadow_reg_errors	8.000s	70.343us	20	20	100.00
V2S	sec_cm_main_config_sparse	aes_smoke	14.000s	140.673us	50	50	100.00
		aes_stress	38.000s	2.788ms	50	50	100.00
		aes_alert_reset	56.000s	3.572ms	50	50	100.00
		aes_core_fi	48.000s	3.658ms	70	70	100.00
V2S	sec_cm_aux_config_shadow	aes_shadow_reg_errors	8.000s	70.343us	20	20	100.00
V2S	sec_cm_aux_config_regwen	aes_readability	9.000s	414.841us	50	50	100.00
		aes_stress	38.000s	2.788ms	50	50	100.00
V2S	sec_cm_key_sideload	aes_stress	38.000s	2.788ms	50	50	100.00
		aes_sideload	11.000s	1.220ms	50	50	100.00
V2S	sec_cm_key_sw_unreadable	aes_readability	9.000s	414.841us	50	50	100.00
V2S	sec_cm_data_reg_sw_unreadable	aes_readability	9.000s	414.841us	50	50	100.00
V2S	sec_cm_key_sec_wipe	aes_readability	9.000s	414.841us	50	50	100.00
V2S	sec_cm_iv_config_sec_wipe	aes_readability	9.000s	414.841us	50	50	100.00
V2S	sec_cm_data_reg_sec_wipe	aes_readability	9.000s	414.841us	50	50	100.00
V2S	sec_cm_data_reg_key_sca	aes_stress	38.000s	2.788ms	50	50	100.00
V2S	sec_cm_key_masking	aes_stress	38.000s	2.788ms	50	50	100.00
V2S	sec_cm_main_fsm_sparse	aes_fi	40.000s	1.920ms	50	50	100.00
V2S	sec_cm_main_fsm_redun	aes_fi	40.000s	1.920ms	50	50	100.00
		aes_control_fi	48.000s	10.013ms	281	300	93.67
		aes_cipher_fi	47.000s	10.014ms	341	350	97.43
		aes_ctr_fi	8.000s	68.241us	49	50	98.00
V2S	sec_cm_cipher_fsm_sparse	aes_fi	40.000s	1.920ms	50	50	100.00
V2S	sec_cm_cipher_fsm_redun	aes_fi	40.000s	1.920ms	50	50	100.00
		aes_control_fi	48.000s	10.013ms	281	300	93.67
		aes_cipher_fi	47.000s	10.014ms	341	350	97.43
V2S	sec_cm_cipher_ctr_redun	aes_cipher_fi	47.000s	10.014ms	341	350	97.43
V2S	sec_cm_ctr_fsm_sparse	aes_fi	40.000s	1.920ms	50	50	100.00
V2S	sec_cm_ctr_fsm_redun	aes_fi	40.000s	1.920ms	50	50	100.00
		aes_control_fi	48.000s	10.013ms	281	300	93.67
		aes_ctr_fi	8.000s	68.241us	49	50	98.00
V2S	sec_cm_ctrl_sparse	aes_fi	40.000s	1.920ms	50	50	100.00
		aes_control_fi	48.000s	10.013ms	281	300	93.67
		aes_cipher_fi	47.000s	10.014ms	341	350	97.43
		aes_ctr_fi	8.000s	68.241us	49	50	98.00
V2S	sec_cm_main_fsm_global_esc	aes_alert_reset	56.000s	3.572ms	50	50	100.00
V2S	sec_cm_main_fsm_local_esc	aes_fi	40.000s	1.920ms	50	50	100.00
		aes_control_fi	48.000s	10.013ms	281	300	93.67
		aes_cipher_fi	47.000s	10.014ms	341	350	97.43
		aes_ctr_fi	8.000s	68.241us	49	50	98.00
V2S	sec_cm_cipher_fsm_local_esc	aes_fi	40.000s	1.920ms	50	50	100.00
		aes_control_fi	48.000s	10.013ms	281	300	93.67
		aes_cipher_fi	47.000s	10.014ms	341	350	97.43
		aes_ctr_fi	8.000s	68.241us	49	50	98.00
V2S	sec_cm_ctr_fsm_local_esc	aes_fi	40.000s	1.920ms	50	50	100.00
		aes_control_fi	48.000s	10.013ms	281	300	93.67
		aes_ctr_fi	8.000s	68.241us	49	50	98.00
V2S	sec_cm_data_reg_local_esc	aes_fi	40.000s	1.920ms	50	50	100.00
		aes_control_fi	48.000s	10.013ms	281	300	93.67
		aes_cipher_fi	47.000s	10.014ms	341	350	97.43
V2S		TOTAL			956	985	97.06
V3	stress_all_with_rand_reset	aes_stress_all_with_rand_reset	19.850m	277.973ms	0	10	0.00
V3		TOTAL			0	10	0.00
		TOTAL			1563	1602	97.57

Testplan Progress

Items	Total	Written	Passing	Progress
V1	7	7	7	100.00
V2	13	13	13	100.00
V2S	11	11	8	72.73
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

Score	Block	Branch	Statement	Expression	Toggle	Fsm	Assertion	CoverGroup
98.59	98.97	97.40	99.45	95.95	97.72	98.52	98.96	96.01

Failure Buckets

Job aes_masked-sim-xcelium_run_default killed due to: Exit reason: User job exceeded runlimit: User job timed out has 20 failures:
- Test aes_control_fi has 14 failures.
  - 3.aes_control_fi.18446629368789292057768671123543068015903697746680659904416321423505868991903
    Log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/3.aes_control_fi/latest/run.log
```
  Job ID: smart:f17e94b4-c67b-4d54-b9cb-a1f2ccbc9071
```
  - 13.aes_control_fi.2019492318420086627947591800660535779674701501960582559330403932383601958451
    Log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/13.aes_control_fi/latest/run.log
```
  Job ID: smart:b3623258-2b4d-47bd-a82d-ee7d7ee7068b
```
  - ... and 12 more failures.
- Test aes_ctr_fi has 1 failures.
  - 44.aes_ctr_fi.83921715459022819674568046499451411019985839822596328262262331894947695148581
    Log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/44.aes_ctr_fi/latest/run.log
```
  Job ID: smart:39fa95f2-1e42-4d5c-b0d9-8d3388e8dde9
```
- Test aes_cipher_fi has 5 failures.
  - 97.aes_cipher_fi.43432351198331522221615924801729838718211151201562144706038460815679731953845
    Log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/97.aes_cipher_fi/latest/run.log
```
  Job ID: smart:4ca50714-0289-49ad-a369-7c672c4dfca9
```
  - 101.aes_cipher_fi.22068993864297534244079677509664323857604144215410689682462519852250307381764
    Log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/101.aes_cipher_fi/latest/run.log
```
  Job ID: smart:5392f3b8-36c5-41da-b63c-d7a184cccef4
```
  - ... and 3 more failures.

UVM_ERROR (uvm_sequencer_base.svh:757) sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'sequencer' for sequence 'sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues has 5 failures:

Test aes_stress_all_with_rand_reset has 5 failures.

0.aes_stress_all_with_rand_reset.31479629179540503798528054137175038633256853966258470630201138344995069222074
Line 1275, in log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/0.aes_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 27727052104 ps: (uvm_sequencer_base.svh:757) uvm_test_top.env.keymgr_sideload_agent.sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'uvm_test_top.env.keymgr_sideload_agent.sequencer' for sequence 'uvm_test_top.env.virtual_sequencer.aes_stress_vseq.sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues
  UVM_INFO @ 27727052104 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

1.aes_stress_all_with_rand_reset.45701397154560401763893157883464140077330343459616326066280469240559455853251
Line 1287, in log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/1.aes_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 12932003230 ps: (uvm_sequencer_base.svh:757) uvm_test_top.env.keymgr_sideload_agent.sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'uvm_test_top.env.keymgr_sideload_agent.sequencer' for sequence 'uvm_test_top.env.virtual_sequencer.aes_stress_vseq.sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues
  UVM_INFO @ 12932003230 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 3 more failures.

UVM_FATAL (aes_control_fi_vseq.sv:62) [aes_control_fi_vseq] wait timeout occurred! has 5 failures:
- Test aes_control_fi has 5 failures.
  - 74.aes_control_fi.53929566317706270411757640538700454862685990543823939762846471845359043673131
    Line 326, in log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/74.aes_control_fi/latest/run.log
```
  UVM_FATAL @ 10025471592 ps: (aes_control_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_control_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10025471592 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 88.aes_control_fi.40521897341327303127919809144140394448966663557520960502308016599163052376601
    Line 313, in log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/88.aes_control_fi/latest/run.log
```
  UVM_FATAL @ 10010853737 ps: (aes_control_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_control_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10010853737 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 3 more failures.
UVM_FATAL (aes_cipher_fi_vseq.sv:62) [aes_cipher_fi_vseq] wait timeout occurred! has 4 failures:
- Test aes_cipher_fi has 4 failures.
  - 3.aes_cipher_fi.26276690905024778211169819964371419743146284527596443194859675413268558304412
    Line 313, in log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/3.aes_cipher_fi/latest/run.log
```
  UVM_FATAL @ 10142826262 ps: (aes_cipher_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_cipher_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10142826262 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 25.aes_cipher_fi.98854427878558713543696404322781688462081859288436478250221541347212082936596
    Line 325, in log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/25.aes_cipher_fi/latest/run.log
```
  UVM_FATAL @ 10013194886 ps: (aes_cipher_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_cipher_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10013194886 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 2 more failures.
UVM_ERROR (cip_base_vseq.sv:828) [aes_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 2 failures:
- Test aes_stress_all_with_rand_reset has 2 failures.
  - 3.aes_stress_all_with_rand_reset.40207987569966596579676900006002155701507095715768750930786314348018975879453
    Line 601, in log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/3.aes_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 9449938095 ps: (cip_base_vseq.sv:828) [uvm_test_top.env.virtual_sequencer.aes_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 9449938095 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 7.aes_stress_all_with_rand_reset.98003576324216140382021932130110018441288310742271476498270742584337292838256
    Line 322, in log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/7.aes_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 645641089 ps: (cip_base_vseq.sv:828) [uvm_test_top.env.virtual_sequencer.aes_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 645641089 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

Exit reason: Error: User command failed UVM_ERROR (uvm_sequencer_base.svh:757) sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'sequencer' for sequence 'sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues has 2 failures:

Test aes_stress_all_with_rand_reset has 2 failures.

4.aes_stress_all_with_rand_reset.101536490018452334468256110020697665303276368269735480293074251580949337242493
Line 1346, in log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/4.aes_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 1319222703 ps: (uvm_sequencer_base.svh:757) uvm_test_top.env.keymgr_sideload_agent.sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'uvm_test_top.env.keymgr_sideload_agent.sequencer' for sequence 'uvm_test_top.env.virtual_sequencer.aes_stress_vseq.sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues
  UVM_INFO @ 1319222703 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

5.aes_stress_all_with_rand_reset.67011894751869528218099508366376517174964338386145518381830457788112201993142
Line 1786, in log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/5.aes_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 277972965654 ps: (uvm_sequencer_base.svh:757) uvm_test_top.env.keymgr_sideload_agent.sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'uvm_test_top.env.keymgr_sideload_agent.sequencer' for sequence 'uvm_test_top.env.virtual_sequencer.aes_stress_vseq.sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues
  UVM_INFO @ 277972965654 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Exit reason: Error: User command failed UVM_FATAL (aes_reseed_vseq.sv:40) [aes_reseed_vseq] Check failed request_seen | finished_all_msgs == *'b* (* [*] vs * [*]) has 1 failures:
- Test aes_stress_all_with_rand_reset has 1 failures.
  - 2.aes_stress_all_with_rand_reset.6745981160532655705243061510832402581507806577019578800261098299987875940418
    Line 543, in log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/2.aes_stress_all_with_rand_reset/latest/run.log
```
  UVM_FATAL @ 2542957389 ps: (aes_reseed_vseq.sv:40) [uvm_test_top.env.virtual_sequencer.aes_reseed_vseq] Check failed request_seen | finished_all_msgs == 1'b1 (0 [0x0] vs 1 [0x1])
  UVM_INFO @ 2542957389 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```