AES/MASKED Simulation Results

Tuesday March 05 2024 20:02:48 UTC

GitHub Revision: `c30684b3ca`

Branch: os_regression

Simulator: XCELIUM

Build randomization enabled with --build-seed 61875946985821051720030118255902427822651914203242934898647746371735217685454

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	wake_up	aes_wake_up	4.000s	81.927us	1	1	100.00
V1	smoke	aes_smoke	18.000s	113.807us	50	50	100.00
V1	csr_hw_reset	aes_csr_hw_reset	3.000s	274.415us	5	5	100.00
V1	csr_rw	aes_csr_rw	6.000s	94.004us	20	20	100.00
V1	csr_bit_bash	aes_csr_bit_bash	11.000s	1.688ms	5	5	100.00
V1	csr_aliasing	aes_csr_aliasing	5.000s	161.640us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	aes_csr_mem_rw_with_rand_reset	8.000s	72.623us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	aes_csr_rw	6.000s	94.004us	20	20	100.00
		aes_csr_aliasing	5.000s	161.640us	5	5	100.00
V1		TOTAL			106	106	100.00
V2	algorithm	aes_smoke	18.000s	113.807us	50	50	100.00
		aes_config_error	15.000s	722.055us	50	50	100.00
		aes_stress	2.883m	5.280ms	50	50	100.00
V2	key_length	aes_smoke	18.000s	113.807us	50	50	100.00
		aes_config_error	15.000s	722.055us	50	50	100.00
		aes_stress	2.883m	5.280ms	50	50	100.00
V2	back2back	aes_stress	2.883m	5.280ms	50	50	100.00
		aes_b2b	42.000s	583.976us	50	50	100.00
V2	backpressure	aes_stress	2.883m	5.280ms	50	50	100.00
V2	multi_message	aes_smoke	18.000s	113.807us	50	50	100.00
		aes_config_error	15.000s	722.055us	50	50	100.00
		aes_stress	2.883m	5.280ms	50	50	100.00
		aes_alert_reset	19.000s	691.740us	50	50	100.00
V2	failure_test	aes_man_cfg_err	14.000s	80.346us	50	50	100.00
		aes_config_error	15.000s	722.055us	50	50	100.00
		aes_alert_reset	19.000s	691.740us	50	50	100.00
V2	trigger_clear_test	aes_clear	8.500m	21.791ms	50	50	100.00
V2	nist_test_vectors	aes_nist_vectors	12.000s	191.471us	1	1	100.00
V2	reset_recovery	aes_alert_reset	19.000s	691.740us	50	50	100.00
V2	stress	aes_stress	2.883m	5.280ms	50	50	100.00
V2	sideload	aes_stress	2.883m	5.280ms	50	50	100.00
		aes_sideload	25.000s	762.380us	50	50	100.00
V2	deinitialization	aes_deinit	12.000s	99.194us	50	50	100.00
V2	stress_all	aes_stress_all	15.717m	28.105ms	10	10	100.00
V2	alert_test	aes_alert_test	8.000s	116.557us	50	50	100.00
V2	tl_d_oob_addr_access	aes_tl_errors	9.000s	1.214ms	20	20	100.00
V2	tl_d_illegal_access	aes_tl_errors	9.000s	1.214ms	20	20	100.00
V2	tl_d_outstanding_access	aes_csr_hw_reset	3.000s	274.415us	5	5	100.00
		aes_csr_rw	6.000s	94.004us	20	20	100.00
		aes_csr_aliasing	5.000s	161.640us	5	5	100.00
		aes_same_csr_outstanding	7.000s	258.158us	20	20	100.00
V2	tl_d_partial_access	aes_csr_hw_reset	3.000s	274.415us	5	5	100.00
		aes_csr_rw	6.000s	94.004us	20	20	100.00
		aes_csr_aliasing	5.000s	161.640us	5	5	100.00
		aes_same_csr_outstanding	7.000s	258.158us	20	20	100.00
V2		TOTAL			501	501	100.00
V2S	reseeding	aes_reseed	1.133m	2.320ms	49	50	98.00
V2S	fault_inject	aes_fi	14.000s	533.827us	50	50	100.00
		aes_control_fi	31.000s	10.012ms	284	300	94.67
		aes_cipher_fi	47.000s	10.007ms	338	350	96.57
V2S	shadow_reg_update_error	aes_shadow_reg_errors	8.000s	76.784us	20	20	100.00
V2S	shadow_reg_read_clear_staged_value	aes_shadow_reg_errors	8.000s	76.784us	20	20	100.00
V2S	shadow_reg_storage_error	aes_shadow_reg_errors	8.000s	76.784us	20	20	100.00
V2S	shadowed_reset_glitch	aes_shadow_reg_errors	8.000s	76.784us	20	20	100.00
V2S	shadow_reg_update_error_with_csr_rw	aes_shadow_reg_errors_with_csr_rw	7.000s	109.529us	20	20	100.00
V2S	tl_intg_err	aes_sec_cm	8.000s	918.637us	5	5	100.00
		aes_tl_intg_err	6.000s	540.747us	20	20	100.00
V2S	sec_cm_bus_integrity	aes_tl_intg_err	6.000s	540.747us	20	20	100.00
V2S	sec_cm_lc_escalate_en_intersig_mubi	aes_alert_reset	19.000s	691.740us	50	50	100.00
V2S	sec_cm_main_config_shadow	aes_shadow_reg_errors	8.000s	76.784us	20	20	100.00
V2S	sec_cm_main_config_sparse	aes_smoke	18.000s	113.807us	50	50	100.00
		aes_stress	2.883m	5.280ms	50	50	100.00
		aes_alert_reset	19.000s	691.740us	50	50	100.00
		aes_core_fi	2.000m	10.040ms	67	70	95.71
V2S	sec_cm_aux_config_shadow	aes_shadow_reg_errors	8.000s	76.784us	20	20	100.00
V2S	sec_cm_aux_config_regwen	aes_readability	8.000s	88.596us	50	50	100.00
		aes_stress	2.883m	5.280ms	50	50	100.00
V2S	sec_cm_key_sideload	aes_stress	2.883m	5.280ms	50	50	100.00
		aes_sideload	25.000s	762.380us	50	50	100.00
V2S	sec_cm_key_sw_unreadable	aes_readability	8.000s	88.596us	50	50	100.00
V2S	sec_cm_data_reg_sw_unreadable	aes_readability	8.000s	88.596us	50	50	100.00
V2S	sec_cm_key_sec_wipe	aes_readability	8.000s	88.596us	50	50	100.00
V2S	sec_cm_iv_config_sec_wipe	aes_readability	8.000s	88.596us	50	50	100.00
V2S	sec_cm_data_reg_sec_wipe	aes_readability	8.000s	88.596us	50	50	100.00
V2S	sec_cm_data_reg_key_sca	aes_stress	2.883m	5.280ms	50	50	100.00
V2S	sec_cm_key_masking	aes_stress	2.883m	5.280ms	50	50	100.00
V2S	sec_cm_main_fsm_sparse	aes_fi	14.000s	533.827us	50	50	100.00
V2S	sec_cm_main_fsm_redun	aes_fi	14.000s	533.827us	50	50	100.00
		aes_control_fi	31.000s	10.012ms	284	300	94.67
		aes_cipher_fi	47.000s	10.007ms	338	350	96.57
		aes_ctr_fi	9.000s	80.757us	50	50	100.00
V2S	sec_cm_cipher_fsm_sparse	aes_fi	14.000s	533.827us	50	50	100.00
V2S	sec_cm_cipher_fsm_redun	aes_fi	14.000s	533.827us	50	50	100.00
		aes_control_fi	31.000s	10.012ms	284	300	94.67
		aes_cipher_fi	47.000s	10.007ms	338	350	96.57
V2S	sec_cm_cipher_ctr_redun	aes_cipher_fi	47.000s	10.007ms	338	350	96.57
V2S	sec_cm_ctr_fsm_sparse	aes_fi	14.000s	533.827us	50	50	100.00
V2S	sec_cm_ctr_fsm_redun	aes_fi	14.000s	533.827us	50	50	100.00
		aes_control_fi	31.000s	10.012ms	284	300	94.67
		aes_ctr_fi	9.000s	80.757us	50	50	100.00
V2S	sec_cm_ctrl_sparse	aes_fi	14.000s	533.827us	50	50	100.00
		aes_control_fi	31.000s	10.012ms	284	300	94.67
		aes_cipher_fi	47.000s	10.007ms	338	350	96.57
		aes_ctr_fi	9.000s	80.757us	50	50	100.00
V2S	sec_cm_main_fsm_global_esc	aes_alert_reset	19.000s	691.740us	50	50	100.00
V2S	sec_cm_main_fsm_local_esc	aes_fi	14.000s	533.827us	50	50	100.00
		aes_control_fi	31.000s	10.012ms	284	300	94.67
		aes_cipher_fi	47.000s	10.007ms	338	350	96.57
		aes_ctr_fi	9.000s	80.757us	50	50	100.00
V2S	sec_cm_cipher_fsm_local_esc	aes_fi	14.000s	533.827us	50	50	100.00
		aes_control_fi	31.000s	10.012ms	284	300	94.67
		aes_cipher_fi	47.000s	10.007ms	338	350	96.57
		aes_ctr_fi	9.000s	80.757us	50	50	100.00
V2S	sec_cm_ctr_fsm_local_esc	aes_fi	14.000s	533.827us	50	50	100.00
		aes_control_fi	31.000s	10.012ms	284	300	94.67
		aes_ctr_fi	9.000s	80.757us	50	50	100.00
V2S	sec_cm_data_reg_local_esc	aes_fi	14.000s	533.827us	50	50	100.00
		aes_control_fi	31.000s	10.012ms	284	300	94.67
		aes_cipher_fi	47.000s	10.007ms	338	350	96.57
V2S		TOTAL			953	985	96.75
V3	stress_all_with_rand_reset	aes_stress_all_with_rand_reset	5.650m	19.226ms	0	10	0.00
V3		TOTAL			0	10	0.00
		TOTAL			1560	1602	97.38

Testplan Progress

Items	Total	Written	Passing	Progress
V1	7	7	7	100.00
V2	13	13	13	100.00
V2S	11	11	7	63.64
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

Score	Block	Branch	Statement	Expression	Toggle	Fsm	Assertion	CoverGroup
98.55	98.92	97.29	99.42	95.82	97.72	97.78	98.96	97.01

Failure Buckets

Job aes_masked-sim-xcelium_run_default killed due to: Exit reason: User job exceeded runlimit: User job timed out has 16 failures:
- Test aes_control_fi has 11 failures.
  - 40.aes_control_fi.71439021586403038614205235020464182387770828084082892401977728564522539089914
    Log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/40.aes_control_fi/latest/run.log
```
  Job ID: smart:34e060ca-1fe0-467d-88c7-c666d86e610a
```
  - 54.aes_control_fi.163122555892602910870622611761246248007150508771419912033910822301254763906
    Log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/54.aes_control_fi/latest/run.log
```
  Job ID: smart:3de617a2-7d80-401c-b380-59c34d8f021c
```
  - ... and 9 more failures.
- Test aes_cipher_fi has 5 failures.
  - 61.aes_cipher_fi.107095931480194459960711053767265369422459796969711139421582100927278396115597
    Log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/61.aes_cipher_fi/latest/run.log
```
  Job ID: smart:6d3aea81-392c-4887-ac11-594a23aa3438
```
  - 171.aes_cipher_fi.93241841534513965455155821253920233239073034722279712902219896117788317948107
    Log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/171.aes_cipher_fi/latest/run.log
```
  Job ID: smart:759a2bf2-8068-4f8c-a686-b146f0205399
```
  - ... and 3 more failures.

UVM_ERROR (uvm_sequencer_base.svh:757) sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'sequencer' for sequence 'sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues has 10 failures:

Test aes_stress_all_with_rand_reset has 10 failures.

0.aes_stress_all_with_rand_reset.12914022913453766780720217764378101388948164179963914122845444221847936745772
Line 1189, in log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/0.aes_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 11359949919 ps: (uvm_sequencer_base.svh:757) uvm_test_top.env.keymgr_sideload_agent.sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'uvm_test_top.env.keymgr_sideload_agent.sequencer' for sequence 'uvm_test_top.env.virtual_sequencer.aes_reseed_vseq.sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues
  UVM_INFO @ 11359949919 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

1.aes_stress_all_with_rand_reset.94168865583741930247509653351440566520901098603020243220889710830489008480039
Line 1021, in log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/1.aes_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 502666422 ps: (uvm_sequencer_base.svh:757) uvm_test_top.env.keymgr_sideload_agent.sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'uvm_test_top.env.keymgr_sideload_agent.sequencer' for sequence 'uvm_test_top.env.virtual_sequencer.aes_stress_vseq.sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues
  UVM_INFO @ 502666422 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 8 more failures.

UVM_FATAL (aes_cipher_fi_vseq.sv:62) [aes_cipher_fi_vseq] wait timeout occurred! has 6 failures:
- Test aes_cipher_fi has 6 failures.
  - 40.aes_cipher_fi.51434552059679949526106791179128229649844422609784287567833522813622014619703
    Line 322, in log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/40.aes_cipher_fi/latest/run.log
```
  UVM_FATAL @ 10015999460 ps: (aes_cipher_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_cipher_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10015999460 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 65.aes_cipher_fi.75532895830618764517710397763595777238533057141156298374207163091569212570923
    Line 330, in log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/65.aes_cipher_fi/latest/run.log
```
  UVM_FATAL @ 10036115792 ps: (aes_cipher_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_cipher_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10036115792 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 4 more failures.
UVM_FATAL (aes_control_fi_vseq.sv:62) [aes_control_fi_vseq] wait timeout occurred! has 5 failures:
- Test aes_control_fi has 5 failures.
  - 88.aes_control_fi.67139999748649798975505212119250023376185081412681836603680198692018126285894
    Line 318, in log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/88.aes_control_fi/latest/run.log
```
  UVM_FATAL @ 10012367764 ps: (aes_control_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_control_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10012367764 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 94.aes_control_fi.69597352473243405638287386371085576329469319888008023801895875575597791095256
    Line 326, in log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/94.aes_control_fi/latest/run.log
```
  UVM_FATAL @ 10016702784 ps: (aes_control_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_control_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10016702784 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 3 more failures.
UVM_FATAL (aes_core_fi_vseq.sv:66) [aes_core_fi_vseq] wait timeout occurred! has 2 failures:
- Test aes_core_fi has 2 failures.
  - 9.aes_core_fi.34528706949857122768518858103939669157921529838921542506640771895379615322975
    Line 323, in log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/9.aes_core_fi/latest/run.log
```
  UVM_FATAL @ 10015276248 ps: (aes_core_fi_vseq.sv:66) [uvm_test_top.env.virtual_sequencer.aes_core_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10015276248 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 62.aes_core_fi.44605697805815232100808368295178994059410822296064183550142976587222891516033
    Line 319, in log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/62.aes_core_fi/latest/run.log
```
  UVM_FATAL @ 10005487786 ps: (aes_core_fi_vseq.sv:66) [uvm_test_top.env.virtual_sequencer.aes_core_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10005487786 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (uvm_sequencer_base.svh:757) sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'sequencer' for sequence 'm_tl_host_base_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues has 1 failures:
- Test aes_cipher_fi has 1 failures.
  - 31.aes_cipher_fi.68381715910040171531837890753376245054823966082294828285435141674570774745869
    Line 316, in log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/31.aes_cipher_fi/latest/run.log
```
  UVM_ERROR @   8506695 ps: (uvm_sequencer_base.svh:757) uvm_test_top.env.m_tl_agent_aes_reg_block.sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'uvm_test_top.env.m_tl_agent_aes_reg_block.sequencer' for sequence 'm_tl_host_base_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues
  UVM_INFO @   8506695 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (aes_reseed_vseq.sv:28) [aes_reseed_vseq] Check failed request_seen == *'b* (* [*] vs * [*]) has 1 failures:
- Test aes_reseed has 1 failures.
  - 49.aes_reseed.115128907548129193952222965557271109106868451791068441553818692849927418355671
    Line 365, in log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/49.aes_reseed/latest/run.log
```
  UVM_FATAL @  20949639 ps: (aes_reseed_vseq.sv:28) [uvm_test_top.env.virtual_sequencer.aes_reseed_vseq] Check failed request_seen == 1'b1 (0 [0x0] vs 1 [0x1])
  UVM_INFO @  20949639 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (csr_utils_pkg.sv:577) [csr_utils::csr_spinwait] timeout aes_reg_block.status.idle (addr=*) == * has 1 failures:
- Test aes_core_fi has 1 failures.
  - 69.aes_core_fi.4926174394435193584399855149236782925251697100911524373567475288748460167612
    Line 314, in log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/69.aes_core_fi/latest/run.log
```
  UVM_FATAL @ 10039936137 ps: (csr_utils_pkg.sv:577) [csr_utils::csr_spinwait] timeout aes_reg_block.status.idle (addr=0xf1fc6884) == 0x0
  UVM_INFO @ 10039936137 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```