AES/MASKED Simulation Results

Sunday March 03 2024 20:02:47 UTC

GitHub Revision: `0cdf265eaa`

Branch: os_regression

Simulator: XCELIUM

Build randomization enabled with --build-seed 82530437672810453765703374940713112405319051694331588453064008042331386550559

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	wake_up	aes_wake_up	3.000s	78.118us	1	1	100.00
V1	smoke	aes_smoke	30.000s	1.575ms	50	50	100.00
V1	csr_hw_reset	aes_csr_hw_reset	13.000s	73.954us	5	5	100.00
V1	csr_rw	aes_csr_rw	4.000s	101.261us	20	20	100.00
V1	csr_bit_bash	aes_csr_bit_bash	10.000s	573.170us	5	5	100.00
V1	csr_aliasing	aes_csr_aliasing	5.000s	108.893us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	aes_csr_mem_rw_with_rand_reset	4.000s	106.582us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	aes_csr_rw	4.000s	101.261us	20	20	100.00
		aes_csr_aliasing	5.000s	108.893us	5	5	100.00
V1		TOTAL			106	106	100.00
V2	algorithm	aes_smoke	30.000s	1.575ms	50	50	100.00
		aes_config_error	14.000s	318.800us	50	50	100.00
		aes_stress	1.283m	2.365ms	50	50	100.00
V2	key_length	aes_smoke	30.000s	1.575ms	50	50	100.00
		aes_config_error	14.000s	318.800us	50	50	100.00
		aes_stress	1.283m	2.365ms	50	50	100.00
V2	back2back	aes_stress	1.283m	2.365ms	50	50	100.00
		aes_b2b	57.000s	659.121us	50	50	100.00
V2	backpressure	aes_stress	1.283m	2.365ms	50	50	100.00
V2	multi_message	aes_smoke	30.000s	1.575ms	50	50	100.00
		aes_config_error	14.000s	318.800us	50	50	100.00
		aes_stress	1.283m	2.365ms	50	50	100.00
		aes_alert_reset	14.000s	235.693us	50	50	100.00
V2	failure_test	aes_man_cfg_err	10.000s	240.973us	50	50	100.00
		aes_config_error	14.000s	318.800us	50	50	100.00
		aes_alert_reset	14.000s	235.693us	50	50	100.00
V2	trigger_clear_test	aes_clear	48.000s	1.358ms	50	50	100.00
V2	nist_test_vectors	aes_nist_vectors	11.000s	567.062us	1	1	100.00
V2	reset_recovery	aes_alert_reset	14.000s	235.693us	50	50	100.00
V2	stress	aes_stress	1.283m	2.365ms	50	50	100.00
V2	sideload	aes_stress	1.283m	2.365ms	50	50	100.00
		aes_sideload	25.000s	1.895ms	50	50	100.00
V2	deinitialization	aes_deinit	21.000s	653.853us	50	50	100.00
V2	stress_all	aes_stress_all	3.483m	23.488ms	10	10	100.00
V2	alert_test	aes_alert_test	8.000s	57.826us	50	50	100.00
V2	tl_d_oob_addr_access	aes_tl_errors	9.000s	264.703us	20	20	100.00
V2	tl_d_illegal_access	aes_tl_errors	9.000s	264.703us	20	20	100.00
V2	tl_d_outstanding_access	aes_csr_hw_reset	13.000s	73.954us	5	5	100.00
		aes_csr_rw	4.000s	101.261us	20	20	100.00
		aes_csr_aliasing	5.000s	108.893us	5	5	100.00
		aes_same_csr_outstanding	4.000s	58.352us	20	20	100.00
V2	tl_d_partial_access	aes_csr_hw_reset	13.000s	73.954us	5	5	100.00
		aes_csr_rw	4.000s	101.261us	20	20	100.00
		aes_csr_aliasing	5.000s	108.893us	5	5	100.00
		aes_same_csr_outstanding	4.000s	58.352us	20	20	100.00
V2		TOTAL			501	501	100.00
V2S	reseeding	aes_reseed	33.000s	1.247ms	50	50	100.00
V2S	fault_inject	aes_fi	16.000s	1.916ms	50	50	100.00
		aes_control_fi	48.000s	10.072ms	275	300	91.67
		aes_cipher_fi	49.000s	10.014ms	337	350	96.29
V2S	shadow_reg_update_error	aes_shadow_reg_errors	4.000s	285.158us	20	20	100.00
V2S	shadow_reg_read_clear_staged_value	aes_shadow_reg_errors	4.000s	285.158us	20	20	100.00
V2S	shadow_reg_storage_error	aes_shadow_reg_errors	4.000s	285.158us	20	20	100.00
V2S	shadowed_reset_glitch	aes_shadow_reg_errors	4.000s	285.158us	20	20	100.00
V2S	shadow_reg_update_error_with_csr_rw	aes_shadow_reg_errors_with_csr_rw	7.000s	70.092us	20	20	100.00
V2S	tl_intg_err	aes_sec_cm	14.000s	838.287us	5	5	100.00
		aes_tl_intg_err	6.000s	162.116us	20	20	100.00
V2S	sec_cm_bus_integrity	aes_tl_intg_err	6.000s	162.116us	20	20	100.00
V2S	sec_cm_lc_escalate_en_intersig_mubi	aes_alert_reset	14.000s	235.693us	50	50	100.00
V2S	sec_cm_main_config_shadow	aes_shadow_reg_errors	4.000s	285.158us	20	20	100.00
V2S	sec_cm_main_config_sparse	aes_smoke	30.000s	1.575ms	50	50	100.00
		aes_stress	1.283m	2.365ms	50	50	100.00
		aes_alert_reset	14.000s	235.693us	50	50	100.00
		aes_core_fi	1.500m	10.011ms	69	70	98.57
V2S	sec_cm_aux_config_shadow	aes_shadow_reg_errors	4.000s	285.158us	20	20	100.00
V2S	sec_cm_aux_config_regwen	aes_readability	8.000s	66.787us	50	50	100.00
		aes_stress	1.283m	2.365ms	50	50	100.00
V2S	sec_cm_key_sideload	aes_stress	1.283m	2.365ms	50	50	100.00
		aes_sideload	25.000s	1.895ms	50	50	100.00
V2S	sec_cm_key_sw_unreadable	aes_readability	8.000s	66.787us	50	50	100.00
V2S	sec_cm_data_reg_sw_unreadable	aes_readability	8.000s	66.787us	50	50	100.00
V2S	sec_cm_key_sec_wipe	aes_readability	8.000s	66.787us	50	50	100.00
V2S	sec_cm_iv_config_sec_wipe	aes_readability	8.000s	66.787us	50	50	100.00
V2S	sec_cm_data_reg_sec_wipe	aes_readability	8.000s	66.787us	50	50	100.00
V2S	sec_cm_data_reg_key_sca	aes_stress	1.283m	2.365ms	50	50	100.00
V2S	sec_cm_key_masking	aes_stress	1.283m	2.365ms	50	50	100.00
V2S	sec_cm_main_fsm_sparse	aes_fi	16.000s	1.916ms	50	50	100.00
V2S	sec_cm_main_fsm_redun	aes_fi	16.000s	1.916ms	50	50	100.00
		aes_control_fi	48.000s	10.072ms	275	300	91.67
		aes_cipher_fi	49.000s	10.014ms	337	350	96.29
		aes_ctr_fi	8.000s	83.288us	50	50	100.00
V2S	sec_cm_cipher_fsm_sparse	aes_fi	16.000s	1.916ms	50	50	100.00
V2S	sec_cm_cipher_fsm_redun	aes_fi	16.000s	1.916ms	50	50	100.00
		aes_control_fi	48.000s	10.072ms	275	300	91.67
		aes_cipher_fi	49.000s	10.014ms	337	350	96.29
V2S	sec_cm_cipher_ctr_redun	aes_cipher_fi	49.000s	10.014ms	337	350	96.29
V2S	sec_cm_ctr_fsm_sparse	aes_fi	16.000s	1.916ms	50	50	100.00
V2S	sec_cm_ctr_fsm_redun	aes_fi	16.000s	1.916ms	50	50	100.00
		aes_control_fi	48.000s	10.072ms	275	300	91.67
		aes_ctr_fi	8.000s	83.288us	50	50	100.00
V2S	sec_cm_ctrl_sparse	aes_fi	16.000s	1.916ms	50	50	100.00
		aes_control_fi	48.000s	10.072ms	275	300	91.67
		aes_cipher_fi	49.000s	10.014ms	337	350	96.29
		aes_ctr_fi	8.000s	83.288us	50	50	100.00
V2S	sec_cm_main_fsm_global_esc	aes_alert_reset	14.000s	235.693us	50	50	100.00
V2S	sec_cm_main_fsm_local_esc	aes_fi	16.000s	1.916ms	50	50	100.00
		aes_control_fi	48.000s	10.072ms	275	300	91.67
		aes_cipher_fi	49.000s	10.014ms	337	350	96.29
		aes_ctr_fi	8.000s	83.288us	50	50	100.00
V2S	sec_cm_cipher_fsm_local_esc	aes_fi	16.000s	1.916ms	50	50	100.00
		aes_control_fi	48.000s	10.072ms	275	300	91.67
		aes_cipher_fi	49.000s	10.014ms	337	350	96.29
		aes_ctr_fi	8.000s	83.288us	50	50	100.00
V2S	sec_cm_ctr_fsm_local_esc	aes_fi	16.000s	1.916ms	50	50	100.00
		aes_control_fi	48.000s	10.072ms	275	300	91.67
		aes_ctr_fi	8.000s	83.288us	50	50	100.00
V2S	sec_cm_data_reg_local_esc	aes_fi	16.000s	1.916ms	50	50	100.00
		aes_control_fi	48.000s	10.072ms	275	300	91.67
		aes_cipher_fi	49.000s	10.014ms	337	350	96.29
V2S		TOTAL			946	985	96.04
V3	stress_all_with_rand_reset	aes_stress_all_with_rand_reset	1.100m	1.668ms	0	10	0.00
V3		TOTAL			0	10	0.00
		TOTAL			1553	1602	96.94

Testplan Progress

Items	Total	Written	Passing	Progress
V1	7	7	7	100.00
V2	13	13	13	100.00
V2S	11	11	8	72.73
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

Score	Block	Branch	Statement	Expression	Toggle	Fsm	Assertion	CoverGroup
98.60	98.95	97.36	99.45	95.91	97.72	100.00	98.96	97.21

Failure Buckets

Job aes_masked-sim-xcelium_run_default killed due to: Exit reason: User job exceeded runlimit: User job timed out has 24 failures:
- Test aes_control_fi has 17 failures.
  - 3.aes_control_fi.103697928261582236494419623238140912050240070776752738904423405040878197478037
    Log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/3.aes_control_fi/latest/run.log
```
  Job ID: smart:d385bf14-9055-44fc-bb3f-0c0d2d3877f7
```
  - 6.aes_control_fi.92031365940928469329618849026961015883369500773847739693177313174853421899360
    Log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/6.aes_control_fi/latest/run.log
```
  Job ID: smart:6ebf5fd6-960d-4196-ac0d-d1cd9722718e
```
  - ... and 15 more failures.
- Test aes_cipher_fi has 7 failures.
  - 76.aes_cipher_fi.22842857567080418289854315316690837308434294995090127563769679360372357431871
    Log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/76.aes_cipher_fi/latest/run.log
```
  Job ID: smart:0470181f-370e-427e-b896-84c51b21d61e
```
  - 96.aes_cipher_fi.83303759591894079609245290291335954375444272979410153076468016900499760940777
    Log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/96.aes_cipher_fi/latest/run.log
```
  Job ID: smart:eaab538d-2832-4056-af3b-e29d10d743fd
```
  - ... and 5 more failures.
UVM_FATAL (aes_control_fi_vseq.sv:62) [aes_control_fi_vseq] wait timeout occurred! has 8 failures:
- Test aes_control_fi has 8 failures.
  - 141.aes_control_fi.73746053556882101783120844775983303471652003677483830304039036951744094725774
    Line 325, in log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/141.aes_control_fi/latest/run.log
```
  UVM_FATAL @ 10016293267 ps: (aes_control_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_control_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10016293267 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 173.aes_control_fi.8675729462866305219930451028411161819850464877567892185709619808626724967234
    Line 330, in log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/173.aes_control_fi/latest/run.log
```
  UVM_FATAL @ 10027516826 ps: (aes_control_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_control_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10027516826 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 6 more failures.
UVM_FATAL (aes_cipher_fi_vseq.sv:62) [aes_cipher_fi_vseq] wait timeout occurred! has 6 failures:
- Test aes_cipher_fi has 6 failures.
  - 30.aes_cipher_fi.51977236309937113395631325327121917660722589233944172660891170653872073899815
    Line 316, in log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/30.aes_cipher_fi/latest/run.log
```
  UVM_FATAL @ 10036114943 ps: (aes_cipher_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_cipher_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10036114943 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 136.aes_cipher_fi.47788426475215856524077161695897067825075833327397899021687259476001978088147
    Line 315, in log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/136.aes_cipher_fi/latest/run.log
```
  UVM_FATAL @ 10009430677 ps: (aes_cipher_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_cipher_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10009430677 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 4 more failures.

Exit reason: Error: User command failed UVM_ERROR (uvm_sequencer_base.svh:757) sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'sequencer' for sequence 'sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues has 5 failures:

Test aes_stress_all_with_rand_reset has 5 failures.

2.aes_stress_all_with_rand_reset.86007887502955790316309546265471148271452063253457504368007320907429237345883
Line 891, in log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/2.aes_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 1372685605 ps: (uvm_sequencer_base.svh:757) uvm_test_top.env.keymgr_sideload_agent.sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'uvm_test_top.env.keymgr_sideload_agent.sequencer' for sequence 'uvm_test_top.env.virtual_sequencer.aes_stress_vseq.sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues
  UVM_INFO @ 1372685605 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

3.aes_stress_all_with_rand_reset.12792312734615258104774177042556040545179121710480890959242256416991889224287
Line 878, in log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/3.aes_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 342494100 ps: (uvm_sequencer_base.svh:757) uvm_test_top.env.keymgr_sideload_agent.sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'uvm_test_top.env.keymgr_sideload_agent.sequencer' for sequence 'uvm_test_top.env.virtual_sequencer.aes_stress_vseq.sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues
  UVM_INFO @ 342494100 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 3 more failures.

UVM_ERROR (uvm_sequencer_base.svh:757) sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'sequencer' for sequence 'sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues has 4 failures:

Test aes_stress_all_with_rand_reset has 4 failures.

0.aes_stress_all_with_rand_reset.67912539127586621115117328999163841993672164833659568118554638910363185516322
Line 499, in log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/0.aes_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 1668201918 ps: (uvm_sequencer_base.svh:757) uvm_test_top.env.keymgr_sideload_agent.sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'uvm_test_top.env.keymgr_sideload_agent.sequencer' for sequence 'uvm_test_top.env.virtual_sequencer.aes_reseed_vseq.sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues
  UVM_INFO @ 1668201918 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

1.aes_stress_all_with_rand_reset.42222620099066794484403363535201977150253948104534635276270989850707686521764
Line 800, in log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/1.aes_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 2491635451 ps: (uvm_sequencer_base.svh:757) uvm_test_top.env.keymgr_sideload_agent.sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'uvm_test_top.env.keymgr_sideload_agent.sequencer' for sequence 'uvm_test_top.env.virtual_sequencer.aes_stress_vseq.sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues
  UVM_INFO @ 2491635451 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 2 more failures.

UVM_FATAL (aes_reseed_vseq.sv:40) [aes_reseed_vseq] Check failed request_seen | finished_all_msgs == *'b* (* [*] vs * [*]) has 1 failures:
- Test aes_stress_all_with_rand_reset has 1 failures.
  - 6.aes_stress_all_with_rand_reset.16488620131590962050585868314673397661067633539357059028860823311096589896736
    Line 628, in log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/6.aes_stress_all_with_rand_reset/latest/run.log
```
  UVM_FATAL @ 1496419382 ps: (aes_reseed_vseq.sv:40) [uvm_test_top.env.virtual_sequencer.aes_reseed_vseq] Check failed request_seen | finished_all_msgs == 1'b1 (0 [0x0] vs 1 [0x1])
  UVM_INFO @ 1496419382 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (aes_core_fi_vseq.sv:89) [aes_core_fi_vseq] wait timeout occurred! has 1 failures:
- Test aes_core_fi has 1 failures.
  - 65.aes_core_fi.48208064051100315057335976255397510764890492832282714308085587067635078208587
    Line 314, in log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/65.aes_core_fi/latest/run.log
```
  UVM_FATAL @ 10010545226 ps: (aes_core_fi_vseq.sv:89) [uvm_test_top.env.virtual_sequencer.aes_core_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10010545226 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```