AES/MASKED Simulation Results

Thursday March 07 2024 20:02:34 UTC

GitHub Revision: `36c168c253`

Branch: os_regression

Simulator: XCELIUM

Build randomization enabled with --build-seed 132539995404104259171688804297348475616986265371189902218943342622053800053

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	wake_up	aes_wake_up	4.000s	62.914us	1	1	100.00
V1	smoke	aes_smoke	16.000s	486.194us	50	50	100.00
V1	csr_hw_reset	aes_csr_hw_reset	3.000s	134.461us	5	5	100.00
V1	csr_rw	aes_csr_rw	5.000s	67.174us	20	20	100.00
V1	csr_bit_bash	aes_csr_bit_bash	10.000s	839.085us	5	5	100.00
V1	csr_aliasing	aes_csr_aliasing	5.000s	136.023us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	aes_csr_mem_rw_with_rand_reset	5.000s	152.346us	19	20	95.00
V1	regwen_csr_and_corresponding_lockable_csr	aes_csr_rw	5.000s	67.174us	20	20	100.00
		aes_csr_aliasing	5.000s	136.023us	5	5	100.00
V1		TOTAL			105	106	99.06
V2	algorithm	aes_smoke	16.000s	486.194us	50	50	100.00
		aes_config_error	24.000s	672.440us	50	50	100.00
		aes_stress	17.000s	241.627us	50	50	100.00
V2	key_length	aes_smoke	16.000s	486.194us	50	50	100.00
		aes_config_error	24.000s	672.440us	50	50	100.00
		aes_stress	17.000s	241.627us	50	50	100.00
V2	back2back	aes_stress	17.000s	241.627us	50	50	100.00
		aes_b2b	51.000s	863.574us	50	50	100.00
V2	backpressure	aes_stress	17.000s	241.627us	50	50	100.00
V2	multi_message	aes_smoke	16.000s	486.194us	50	50	100.00
		aes_config_error	24.000s	672.440us	50	50	100.00
		aes_stress	17.000s	241.627us	50	50	100.00
		aes_alert_reset	42.000s	3.813ms	50	50	100.00
V2	failure_test	aes_man_cfg_err	6.000s	200.317us	50	50	100.00
		aes_config_error	24.000s	672.440us	50	50	100.00
		aes_alert_reset	42.000s	3.813ms	50	50	100.00
V2	trigger_clear_test	aes_clear	53.000s	2.659ms	50	50	100.00
V2	nist_test_vectors	aes_nist_vectors	19.000s	305.058us	1	1	100.00
V2	reset_recovery	aes_alert_reset	42.000s	3.813ms	50	50	100.00
V2	stress	aes_stress	17.000s	241.627us	50	50	100.00
V2	sideload	aes_stress	17.000s	241.627us	50	50	100.00
		aes_sideload	24.000s	3.126ms	50	50	100.00
V2	deinitialization	aes_deinit	2.333m	4.822ms	50	50	100.00
V2	stress_all	aes_stress_all	2.017m	5.137ms	10	10	100.00
V2	alert_test	aes_alert_test	6.000s	186.060us	50	50	100.00
V2	tl_d_oob_addr_access	aes_tl_errors	6.000s	207.512us	20	20	100.00
V2	tl_d_illegal_access	aes_tl_errors	6.000s	207.512us	20	20	100.00
V2	tl_d_outstanding_access	aes_csr_hw_reset	3.000s	134.461us	5	5	100.00
		aes_csr_rw	5.000s	67.174us	20	20	100.00
		aes_csr_aliasing	5.000s	136.023us	5	5	100.00
		aes_same_csr_outstanding	4.000s	124.003us	20	20	100.00
V2	tl_d_partial_access	aes_csr_hw_reset	3.000s	134.461us	5	5	100.00
		aes_csr_rw	5.000s	67.174us	20	20	100.00
		aes_csr_aliasing	5.000s	136.023us	5	5	100.00
		aes_same_csr_outstanding	4.000s	124.003us	20	20	100.00
V2		TOTAL			501	501	100.00
V2S	reseeding	aes_reseed	38.000s	1.316ms	50	50	100.00
V2S	fault_inject	aes_fi	17.000s	1.008ms	50	50	100.00
		aes_control_fi	28.000s	10.030ms	279	300	93.00
		aes_cipher_fi	50.000s	10.007ms	340	350	97.14
V2S	shadow_reg_update_error	aes_shadow_reg_errors	4.000s	221.525us	20	20	100.00
V2S	shadow_reg_read_clear_staged_value	aes_shadow_reg_errors	4.000s	221.525us	20	20	100.00
V2S	shadow_reg_storage_error	aes_shadow_reg_errors	4.000s	221.525us	20	20	100.00
V2S	shadowed_reset_glitch	aes_shadow_reg_errors	4.000s	221.525us	20	20	100.00
V2S	shadow_reg_update_error_with_csr_rw	aes_shadow_reg_errors_with_csr_rw	5.000s	72.640us	20	20	100.00
V2S	tl_intg_err	aes_sec_cm	8.000s	1.309ms	5	5	100.00
		aes_tl_intg_err	5.000s	235.120us	20	20	100.00
V2S	sec_cm_bus_integrity	aes_tl_intg_err	5.000s	235.120us	20	20	100.00
V2S	sec_cm_lc_escalate_en_intersig_mubi	aes_alert_reset	42.000s	3.813ms	50	50	100.00
V2S	sec_cm_main_config_shadow	aes_shadow_reg_errors	4.000s	221.525us	20	20	100.00
V2S	sec_cm_main_config_sparse	aes_smoke	16.000s	486.194us	50	50	100.00
		aes_stress	17.000s	241.627us	50	50	100.00
		aes_alert_reset	42.000s	3.813ms	50	50	100.00
		aes_core_fi	1.467m	10.007ms	68	70	97.14
V2S	sec_cm_aux_config_shadow	aes_shadow_reg_errors	4.000s	221.525us	20	20	100.00
V2S	sec_cm_aux_config_regwen	aes_readability	5.000s	179.145us	49	50	98.00
		aes_stress	17.000s	241.627us	50	50	100.00
V2S	sec_cm_key_sideload	aes_stress	17.000s	241.627us	50	50	100.00
		aes_sideload	24.000s	3.126ms	50	50	100.00
V2S	sec_cm_key_sw_unreadable	aes_readability	5.000s	179.145us	49	50	98.00
V2S	sec_cm_data_reg_sw_unreadable	aes_readability	5.000s	179.145us	49	50	98.00
V2S	sec_cm_key_sec_wipe	aes_readability	5.000s	179.145us	49	50	98.00
V2S	sec_cm_iv_config_sec_wipe	aes_readability	5.000s	179.145us	49	50	98.00
V2S	sec_cm_data_reg_sec_wipe	aes_readability	5.000s	179.145us	49	50	98.00
V2S	sec_cm_data_reg_key_sca	aes_stress	17.000s	241.627us	50	50	100.00
V2S	sec_cm_key_masking	aes_stress	17.000s	241.627us	50	50	100.00
V2S	sec_cm_main_fsm_sparse	aes_fi	17.000s	1.008ms	50	50	100.00
V2S	sec_cm_main_fsm_redun	aes_fi	17.000s	1.008ms	50	50	100.00
		aes_control_fi	28.000s	10.030ms	279	300	93.00
		aes_cipher_fi	50.000s	10.007ms	340	350	97.14
		aes_ctr_fi	15.000s	595.731us	50	50	100.00
V2S	sec_cm_cipher_fsm_sparse	aes_fi	17.000s	1.008ms	50	50	100.00
V2S	sec_cm_cipher_fsm_redun	aes_fi	17.000s	1.008ms	50	50	100.00
		aes_control_fi	28.000s	10.030ms	279	300	93.00
		aes_cipher_fi	50.000s	10.007ms	340	350	97.14
V2S	sec_cm_cipher_ctr_redun	aes_cipher_fi	50.000s	10.007ms	340	350	97.14
V2S	sec_cm_ctr_fsm_sparse	aes_fi	17.000s	1.008ms	50	50	100.00
V2S	sec_cm_ctr_fsm_redun	aes_fi	17.000s	1.008ms	50	50	100.00
		aes_control_fi	28.000s	10.030ms	279	300	93.00
		aes_ctr_fi	15.000s	595.731us	50	50	100.00
V2S	sec_cm_ctrl_sparse	aes_fi	17.000s	1.008ms	50	50	100.00
		aes_control_fi	28.000s	10.030ms	279	300	93.00
		aes_cipher_fi	50.000s	10.007ms	340	350	97.14
		aes_ctr_fi	15.000s	595.731us	50	50	100.00
V2S	sec_cm_main_fsm_global_esc	aes_alert_reset	42.000s	3.813ms	50	50	100.00
V2S	sec_cm_main_fsm_local_esc	aes_fi	17.000s	1.008ms	50	50	100.00
		aes_control_fi	28.000s	10.030ms	279	300	93.00
		aes_cipher_fi	50.000s	10.007ms	340	350	97.14
		aes_ctr_fi	15.000s	595.731us	50	50	100.00
V2S	sec_cm_cipher_fsm_local_esc	aes_fi	17.000s	1.008ms	50	50	100.00
		aes_control_fi	28.000s	10.030ms	279	300	93.00
		aes_cipher_fi	50.000s	10.007ms	340	350	97.14
		aes_ctr_fi	15.000s	595.731us	50	50	100.00
V2S	sec_cm_ctr_fsm_local_esc	aes_fi	17.000s	1.008ms	50	50	100.00
		aes_control_fi	28.000s	10.030ms	279	300	93.00
		aes_ctr_fi	15.000s	595.731us	50	50	100.00
V2S	sec_cm_data_reg_local_esc	aes_fi	17.000s	1.008ms	50	50	100.00
		aes_control_fi	28.000s	10.030ms	279	300	93.00
		aes_cipher_fi	50.000s	10.007ms	340	350	97.14
V2S		TOTAL			951	985	96.55
V3	stress_all_with_rand_reset	aes_stress_all_with_rand_reset	5.883m	42.018ms	0	10	0.00
V3		TOTAL			0	10	0.00
		TOTAL			1557	1602	97.19

Testplan Progress

Items	Total	Written	Passing	Progress
V1	7	7	6	85.71
V2	13	13	13	100.00
V2S	11	11	7	63.64
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

Score	Block	Branch	Statement	Expression	Toggle	Fsm	Assertion	CoverGroup
98.53	98.93	97.31	99.43	95.71	97.64	98.52	98.96	95.81

Failure Buckets

Job aes_masked-sim-xcelium_run_default killed due to: Exit reason: User job exceeded runlimit: User job timed out has 26 failures:
- Test aes_control_fi has 19 failures.
  - 12.aes_control_fi.51722091051417011478313245967447849896135861700068104979017594650254187601352
    Log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/12.aes_control_fi/latest/run.log
```
  Job ID: smart:1e4cd210-0dc0-4bb7-a1c2-4ba7aa73922b
```
  - 19.aes_control_fi.63669656343149769364910332764853303274831917748315203782694003779703718178445
    Log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/19.aes_control_fi/latest/run.log
```
  Job ID: smart:6e5f5ef4-c4fc-4c32-8cdd-a645c450eb68
```
  - ... and 17 more failures.
- Test aes_cipher_fi has 7 failures.
  - 18.aes_cipher_fi.35953809255004491169438144672366709806610818947077513866615339519545425991398
    Log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/18.aes_cipher_fi/latest/run.log
```
  Job ID: smart:d27518a2-f685-41f5-a059-92a23b82b5ae
```
  - 71.aes_cipher_fi.37672654288654600483374103840593615827523093745025975867815077427575317169369
    Log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/71.aes_cipher_fi/latest/run.log
```
  Job ID: smart:42c304c8-80f1-4053-b9f0-a71575ff78b1
```
  - ... and 5 more failures.

UVM_ERROR (uvm_sequencer_base.svh:757) sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'sequencer' for sequence 'sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues has 8 failures:

Test aes_stress_all_with_rand_reset has 8 failures.

0.aes_stress_all_with_rand_reset.33550111648831459411353770860219535451114678866424085320878098821124501728867
Line 1239, in log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/0.aes_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 1056459647 ps: (uvm_sequencer_base.svh:757) uvm_test_top.env.keymgr_sideload_agent.sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'uvm_test_top.env.keymgr_sideload_agent.sequencer' for sequence 'uvm_test_top.env.virtual_sequencer.aes_stress_vseq.sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues
  UVM_INFO @ 1056459647 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

1.aes_stress_all_with_rand_reset.86493369290378263891567856065767197209680372039122572611176835854988015922754
Line 1642, in log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/1.aes_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 3571249841 ps: (uvm_sequencer_base.svh:757) uvm_test_top.env.keymgr_sideload_agent.sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'uvm_test_top.env.keymgr_sideload_agent.sequencer' for sequence 'uvm_test_top.env.virtual_sequencer.aes_stress_vseq.sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues
  UVM_INFO @ 3571249841 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 6 more failures.

UVM_FATAL (aes_cipher_fi_vseq.sv:62) [aes_cipher_fi_vseq] wait timeout occurred! has 3 failures:
- Test aes_cipher_fi has 3 failures.
  - 34.aes_cipher_fi.56744706335680979940835479782822892126156330647623489623433264370725518836516
    Line 315, in log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/34.aes_cipher_fi/latest/run.log
```
  UVM_FATAL @ 10007160489 ps: (aes_cipher_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_cipher_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10007160489 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 161.aes_cipher_fi.76302389225771823069039945882847853771241218089479703571017025700975075870370
    Line 327, in log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/161.aes_cipher_fi/latest/run.log
```
  UVM_FATAL @ 10031798602 ps: (aes_cipher_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_cipher_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10031798602 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 1 more failures.

Exit reason: Error: User command failed UVM_ERROR (uvm_sequencer_base.svh:757) sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'sequencer' for sequence 'sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues has 2 failures:

Test aes_stress_all_with_rand_reset has 2 failures.

2.aes_stress_all_with_rand_reset.98981306394962026681961658082444343295083128886155013289893093897330758395756
Line 952, in log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/2.aes_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 1750760602 ps: (uvm_sequencer_base.svh:757) uvm_test_top.env.keymgr_sideload_agent.sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'uvm_test_top.env.keymgr_sideload_agent.sequencer' for sequence 'uvm_test_top.env.virtual_sequencer.aes_stress_vseq.sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues
  UVM_INFO @ 1750760602 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

9.aes_stress_all_with_rand_reset.48649647129115136269736877346937835757188385130248890865322013413386835181225
Line 619, in log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/9.aes_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 230376759 ps: (uvm_sequencer_base.svh:757) uvm_test_top.env.keymgr_sideload_agent.sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'uvm_test_top.env.keymgr_sideload_agent.sequencer' for sequence 'uvm_test_top.env.virtual_sequencer.aes_stress_vseq.sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues
  UVM_INFO @ 230376759 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_FATAL (aes_core_fi_vseq.sv:66) [aes_core_fi_vseq] wait timeout occurred! has 2 failures:
- Test aes_core_fi has 2 failures.
  - 37.aes_core_fi.52279540182881036668672396259408127014758635509102968842696568214962338142213
    Line 313, in log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/37.aes_core_fi/latest/run.log
```
  UVM_FATAL @ 10006818586 ps: (aes_core_fi_vseq.sv:66) [uvm_test_top.env.virtual_sequencer.aes_core_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10006818586 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 38.aes_core_fi.61775087592901725020571878145027936352973290447400640612742393879198572705967
    Line 321, in log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/38.aes_core_fi/latest/run.log
```
  UVM_FATAL @ 10021669509 ps: (aes_core_fi_vseq.sv:66) [uvm_test_top.env.virtual_sequencer.aes_core_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10021669509 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (aes_control_fi_vseq.sv:62) [aes_control_fi_vseq] wait timeout occurred! has 2 failures:
- Test aes_control_fi has 2 failures.
  - 139.aes_control_fi.16788753818633949202023232703388191141551741307617293627734042438647430462706
    Line 314, in log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/139.aes_control_fi/latest/run.log
```
  UVM_FATAL @ 10029807683 ps: (aes_control_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_control_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10029807683 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 171.aes_control_fi.16441473130011546519135355092445148923739370061114813304027219172793114383851
    Line 324, in log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/171.aes_control_fi/latest/run.log
```
  UVM_FATAL @ 10013139820 ps: (aes_control_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_control_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10013139820 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (aes_readability_vseq.sv:114) virtual_sequencer [aes_readability_vseq] ----| Data reg was did not clear |---- has 1 failures:
- Test aes_readability has 1 failures.
  - 8.aes_readability.22141932284381363064460519966825287237247617871398725227369918269742866367190
    Line 307, in log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/8.aes_readability/latest/run.log
```
  UVM_FATAL @   5932439 ps: (aes_readability_vseq.sv:114) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.aes_readability_vseq] ----| Data reg was did not clear |----
  UVM_INFO @   5932439 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (cip_base_vseq.sv:828) [aes_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 1 failures:
- Test aes_csr_mem_rw_with_rand_reset has 1 failures.
  - 12.aes_csr_mem_rw_with_rand_reset.82765931953062407983931338129537624133773555782575988407151643537528425332255
    Line 285, in log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/12.aes_csr_mem_rw_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 106133830 ps: (cip_base_vseq.sv:828) [uvm_test_top.env.virtual_sequencer.aes_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 106133830 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```